Resistive Memory DBI Control for Write Disturbance Mitigation
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Solution Overview
Problem
Resistive memory devices, such as phase-change random access memory (PRAM), face issues with data retention due to drift phenomena and disturbances like inhibit and thermal disturbances, which lead to increased probability of malfunction during write operations, especially as memory cell density increases.
Innovation Solution
A memory system that performs data bus inversion (DBI) operations based on the access history of resistive memory cells, considering inhibit and thermal disturbances, by generating DBI information and using it to selectively invert write data, thereby reducing errors and improving write operation performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cell density is increased to meet high capacity demands, then storage capacity is improved, but the probability of malfunction during write operations increases due to inhibit and thermal disturbances
Solution Approach 1:
The system performs preliminary actions by counting access numbers of word lines, bit lines, and unit blocks before write operations occur. This historical data is stored and used to predict potential disturbances in advance, allowing the system to take preventive measures during actual write operations to maintain reliability despite high density
Solution Approach 2:
The system implements feedback mechanisms by continuously monitoring and counting access numbers of word lines, bit lines, and unit blocks. This feedback information is used to dynamically determine write operation parameters and generate DBI information, creating a closed-loop control system that adapts to actual usage patterns to prevent disturbances
2Reliability
If data bus inversion (DBI) operation is performed based on access history to reduce errors, then write operation reliability is improved, but device complexity increases due to additional counting blocks and control logic
Solution Approach 1:
The control circuit is segmented into distinct functional blocks: line counting block for monitoring word line and bit line accesses, block counting block for monitoring unit block accesses, and DBI control block for processing the counted information. This segmentation allows each block to perform its specific function independently, making the complex system more modular and manageable while achieving the reliability improvement
Data Source
AI summary
A memory system includes a resistive memory device comprising a memory cell array including a plurality of resistive memory cells and a peripheral circuit; and a memory controller suitable for generating data bus inversion (DBI) information which corresponds to write data based on an access history of the resistive memory cell corresponding to an address of the write data, and providing the DBI information, the address and the write data to the peripheral circuit, wherein the peripheral circuit is suitable for selectively inverting the write data based on the DBI information and writing the selectively inverted write data in a memory cell selected according to the address among the resistive memory cells.