Resistive-Memory Neuromorphic Circuits for Parallel Dot-Product Computing
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Solution Overview
Problem
Conventional microprocessor technology is limited by its chronological operation execution, leading to inefficiencies in computation power, size, and power consumption, making it unsuitable for applications requiring high computational power like image recognition, and large-scale neuromorphic computing networks are physically large and power-intensive, limiting their implementation in industries such as biomedical, military, and mobile devices.
Innovation Solution
Analog neuromorphic circuits utilizing resistive memories with variable resistance values and a controller to perform parallel multiplication and addition operations, enabling efficient computation with minimal power and space, by configuring resistive memories in a crossbar layout and using a controller to convert resistance values into non-binary values for dot-product operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional microprocessor technology is used to perform operations in chronological order, then the system is simple to implement, but the computation power is limited and power consumption is high
Solution Approach 1:
The patent replaces conventional digital microprocessor operations with analog circuit operations. Resistive memories store matrix values as resistance values, and dot-product operations are performed through analog multiplication of input voltages by resistance values, with results summed through parallel circuit paths. This analog approach enables simultaneous execution of multiple operations, dramatically increasing computation power while reducing power consumption compared to chronological digital processing.
2Power
If conventional neuromorphic computing networks are implemented in large scale computer clusters, then the computation power is sufficient for applications like image recognition, but the physical space required is significant and power consumption is high
Solution Approach 1:
The patent merges multiple functions into a single integrated circuit structure. The resistive memory array simultaneously serves as both storage for matrix values and as the computational element for performing dot-product operations. By combining storage and computation in one physical location using the same hardware components, the system achieves high computation power in a compact form factor, eliminating the need for large-scale computer clusters.
Solution Approach 2:
The patent transitions from sequential one-dimensional processing to parallel two-dimensional array processing. The resistive memories are arranged in a crossbar array where rows and columns enable simultaneous multiplication and addition operations. This dimensional transformation allows N×M dot-product operations to be performed in parallel rather than sequentially, dramatically reducing the physical space and power required for equivalent computation power.
3Use of energy by stationary object
If resistive memories with finite range resistance values are used, then the hardware is simple and power consumption is low, but the precision of representing non-binary matrix values is limited
Solution Approach 1:
The patent uses pairs of resistive memories to represent single matrix values, where each resistive memory provides a positive resistance value from a finite range. By combining two such values through the analog computation process, the system effectively represents a broader range of matrix values including negative values and finer precision steps. This partial action approach maintains simple hardware with low power consumption while achieving the necessary precision for neural network computations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides significantly more computational power with reduced power consumption and size, allowing implementation in compact devices capable of complex computations like image recognition and learning algorithms, suitable for applications in robotics, security, and medical fields.
Implementation Method 1
Each resistive memory is configured to provide a resistance value to each corresponding input voltage. Each resistance value is a positive resistance value selected from a finite range of resistance values.
Implementation Method 2
The controller is configured to convert each pair of resistance values from a pair of resistance values selected from the finite range of resistance values to a single non-binary value. Each single non-binary value is mapped to a matrix value included in the matrix that is incorporated into the dot-product operation with the vector values included in the vector.
Data Source
AI summary
An analog neuromorphic circuit is disclosed having resistive memories that provide a resistance to each corresponding input voltage signal. Input voltages are applied to the analog neuromorphic circuit. Each input voltage represents a vector value that is a non-binary value included in a vector that is incorporated into a dot-product operation with weighted matrix values included in a weighted matrix. A controller pairs each resistive memory with another resistive memory. The controller converts each pair of resistance values to a single non-binary value. Each single non-binary value is mapped to a weighted matrix value included in the weighted matrix that is incorporated into the dot-product operation with the vector values included in the vector. The controller generates dot-product operation values from the dot-product operation with the vector and the weighted matrix where each dot-product operation is a non-binary value.