Resistive Memory Device Resistance Drift Control
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Solution Overview
Problem
Resistive memory devices face a challenge with resistance drift, which causes the resistance value of memory cells to increase over time, leading to a short retention time and instability in data storage, especially in multi-level cells, making it difficult to maintain stable operation and store multiple bits of data effectively.
Innovation Solution
The implementation of a resistive memory device with a controller that performs sequential programming and verification operations, where the verify read operation is delayed to allow for resistance drift to occur, reducing the impact of resistance increase and extending data retention time by adjusting the time interval between programming and verification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If verify read operation is performed immediately after program operation, then programming speed is improved, but resistance drift causes verification failure and short retention time
Solution Approach 1:
The patent applies preliminary action by performing the verify read operation after a predetermined time has elapsed following the program operation. This timing adjustment allows resistance drift to occur before verification, ensuring that the read operation reflects the actual stable state of the memory cell rather than the transient state immediately after programming. This resolves the contradiction by sacrificing immediate verification speed for reliable data retention assessment.
2Duration of action of stationary object
If resistance drift is reduced by adjusting verify timing, then data retention time is extended, but write operation time increases due to delayed verification
Solution Approach 1:
The patent implements periodic action by establishing a predetermined time interval between the program operation and the verify read operation. This standardized timing approach allows resistance drift to occur systematically before verification, ensuring consistent and reliable retention time measurement across all write operations. The periodic timing structure balances the need for accurate retention assessment with operational efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces resistance drift, allowing for longer data retention times and maintaining stable operation of resistive memory devices, even when storing multiple bits of data, by ensuring that verify operations are performed after sufficient resistance drift has occurred, thus preventing premature failure in read operations.
Implementation Method 1
a write current may be applied to the resistance element from a bit line to change the resistance state of the resistance element into a crystal state (low resistance state) or amorphous state (high resistance state)
Data Source
AI summary
A resistive memory device includes a memory cell array including a plurality of resistive memory cells, an address decoder suitable for decoding an address signal and selecting the resistive memory cells, a read/write control circuit suitable for programming data to the memory cell array or reading data from the memory cell array, a voltage generator suitable for generating operation voltages and providing the operation voltages to the address decoder and a controller suitable for controlling the address decoder, the read/write control circuit, and the voltage generator to perform a write operation in response to a write command and a plurality of write data.