Resistive Memory Read Method via Dual Voltage Snap-Back

Solution Overview

Problem

Resistive memory devices face challenges in accurately reading data due to sneak currents and leakage currents between neighboring memory cells in three-dimensional cross-point array structures, which affect the reliability of resistance state determination.

Innovation Solution

A method involving a memory cell with a selection element exhibiting snap-back behavior, where first and second read voltages are applied to measure cell currents within specific voltage ranges, allowing for the determination of resistance states based on the characteristics of these currents.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If three-dimensional cross-point array structure is used for high integration, then memory device integration is improved, but sneak currents and leakage currents between neighboring memory cells increase

Engineering Contradiction:

Improvememory device integrationVSAvoidresistance state determination reliability

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The patent segments the reading process into multiple distinct steps: applying a first read voltage to measure first cell current, then applying a second read voltage to measure second cell current. This segmentation allows separate measurement of signal current and sneak/leakage currents, enabling their distinction and improving reliability while maintaining high integration.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent changes the voltage parameter between measurements by applying two different read voltages (first read voltage and second read voltage) with different magnitudes. This parameter change enables differentiation between the resistance state signal and sneak/leakage currents based on their different voltage dependencies, resolving the reliability issue in highly integrated structures.

Inventive Principle:

Principle #35Parameter changes

2Ease of operation

If single read voltage measurement is used, then reading process is simple, but accuracy of resistance state determination is reduced due to sneak and leakage currents

Engineering Contradiction:

Improvereading process simplicityVSAvoidresistance state determination accuracy

Core Design Contradiction:

Ease of operationVSMeasurement precision

Solution Approach 1:

The patent segments the reading process into multiple distinct steps: applying a first read voltage to measure first cell current, then applying a second read voltage to measure second cell current. This segmentation allows separate measurement of signal current and sneak/leakage currents, enabling their distinction and improving reliability while maintaining high integration.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent changes the voltage parameter between measurements by applying two different read voltages (first read voltage and second read voltage) with different magnitudes. This parameter change enables differentiation between the resistance state signal and sneak/leakage currents based on their different voltage dependencies, resolving the reliability issue in highly integrated structures.

Inventive Principle:

Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances the accuracy of resistance state determination by minimizing errors from sneak and leakage currents, thereby improving the reliability of data reading in resistive memory devices.

Implementation Method 1

the selection element exhibits a snap-back behavior on a current-voltage sweep curve for the memory cell

Methodology Applied

Scientific EffectSnap-back behavior:

Data Source

PatentUS10460799B2Method of reading resistive memory device

Publication Date: 2019.10.29 SK HYNIX INC

AI summary

In a method of reading a resistive memory device according to an embodiment, a memory cell including a selection element and a variable resistance element is prepared. The selection element exhibits a snap-back behavior on a current-voltage sweep curve for the memory cell. First and second read voltages to be applied to the memory cell are determined within a voltage range in which the selection element maintains a turned-on state. The magnitude of the second read voltage is less than that of the first read voltage and selected in a voltage range in which the selection element exhibits the snap-back behavior. The first read voltage is applied to the memory cell to measure a first cell current. The second read voltage is applied to the memory cell to measure a second cell current. A resistance state stored in the memory cell is determined based on the first cell current and the second cell current.