Resistive Memory Erasing via Dynamic Voltage Pulses
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Solution Overview
Problem
Existing resistive memory devices face issues with excessive electrical stress during erasing due to inconsistent erasing potentials across devices in an array, leading to potential device overstress and inefficient switching operations.
Innovation Solution
The method involves applying successive increasing voltages or current limits across resistive memory devices, with state checks after each pulse to ensure the minimum number of pulses are used to achieve the erased state, thereby avoiding excessive electrical stress and promoting efficient switching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a fixed number of voltage pulses at constant height are applied for erasing, then the erasing process is simple to implement, but excessive electrical stress occurs due to inconsistent erasing potentials across devices
Solution Approach 1:
The patent applies dynamic voltage adjustment during the erasing process. Instead of using fixed constant-height voltage pulses, the method employs successive voltage pulses with increasing amplitude. The voltage starts at a lower level and progressively increases until the erasing threshold is reached, allowing each device to receive only the minimum necessary electrical stress for erasure without excessive potential
Solution Approach 2:
The patent changes the voltage parameter dynamically during the erasing operation. By varying the voltage amplitude across successive pulses rather than maintaining a constant value, the system adapts to the specific erasing requirements of each device, preventing both insufficient erasure and excessive electrical stress
2Reliability
If higher gate voltage is applied during erase to provide higher current, then the erasing effectiveness is improved, but energy consumption increases
Solution Approach 1:
The patent applies partial action by using successive voltage pulses that gradually increase in amplitude. Rather than applying a single high-voltage pulse that would guarantee erasure but consume excessive energy, the method uses multiple pulses at progressively higher levels, applying only the minimum necessary energy to achieve the erasing effect
Solution Approach 2:
The erasing process employs periodic voltage pulses rather than a continuous high-voltage application. The successive pulsing approach allows the device to respond to each pulse, with the voltage level adjusted between pulses, reducing overall energy consumption while maintaining effective erasure
3Object-affected harmful factors
If successive increasing voltages are applied to avoid excessive stress, then device safety is improved, but the erasing process time increases
Solution Approach 1:
The patent incorporates feedback mechanisms to detect when erasing is complete. By monitoring device state after successive voltage pulses, the system can terminate the erasing process as soon as the erasing threshold is reached, preventing unnecessary delay while ensuring complete erasure. This feedback-driven approach optimizes both time and electrical stress
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures proper erasing while minimizing unnecessary electrical potential, reducing energy waste and operation time, and allows for efficient switching operations by using the minimum number of pulses required to achieve the targeted erased state.
Implementation Method 1
a programming voltage Vpg is applied to the electrode 36, so that an electrical potential is applied across the memory device 30 from a higher to a lower potential in the direction from electrode 36 to electrode 32. This voltage Vpg is sufficient to cause charge carriers to be moved into the insulating layer 34, causing the insulating layer 34 (and the overall memory device 30) to rapidly switch to a low-resistance or conductive state
Implementation Method 2
Upon removal of such potential, the charge carriers moved into the insulating layer 34 during the programming step remain therein, so that the insulating layer 34 (and memory device 30) remain in a conductive or low-resistance state
Implementation Method 3
a positive voltage Ver is applied to the electrode 36, so that an electrical potential is applied across the memory device 30 from a higher to a lower electrical potential in the same direction as in programming the device 30. This potential Ver is sufficient to cause charge carriers to move from the insulating layer 34, in turn causing the insulating layer 34 (and the overall memory device 30) to be in a high-resistance or substantially non-conductive state
Data Source
AI summary
In a first method of erasing a resistive memory device, an electrical potential is applied to the gate of a transistor in series with the resistive memory device, and successive increasing currents are provided through the resistive memory device by means of providing successive increasing electrical potentials across the resistive memory device. In a second method of erasing a resistive memory device, an electrical potential is applied across the resistive memory device, and successive increasing currents are provided through the resistive memory device by means of providing successive increasing electrical potentials to the gate of a transistor in series with the resistive memory device.