Resistive Memory ECC Writes for Narrower Resistance Distribution
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Solution Overview
Problem
Resistive memory devices face challenges in maintaining data accuracy and error correction due to the variability in resistance levels, which can lead to errors during data storage and retrieval, limiting their yield and reliability.
Innovation Solution
Implementing Error Check and Correction (ECC) write and read operations with stricter conditions than standard data operations, using incremental step pulses with smaller intervals and higher maximum voltages to maintain a narrower resistance distribution for ECC code storage, ensuring higher accuracy and reliability of ECC code operations compared to data operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If standard data write operations are used for writing ECC codes, then writing speed is maintained, but error generation risk increases
Solution Approach 1:
The patent applies parameter changes by modifying write operation parameters specifically for ECC code writing. The controller adjusts voltage levels, pulse widths, or current magnitudes during ECC code write operations to achieve more reliable programming with reduced error generation risk, while using standard parameters for regular data writing to maintain speed.
Solution Approach 2:
The patent segments the write operation into two distinct modes: standard data write operations for regular memory cells and specialized ECC code write operations for error correction code cells. This segmentation allows different operational parameters and verification procedures to be applied to each type of data, optimizing both speed and reliability for their respective purposes.
2Reliability
If ECC function is implemented to detect and correct errors, then data reliability improves, but system complexity increases
Solution Approach 1:
The patent implements self-service by enabling the memory system to automatically detect, locate, and correct errors in stored data using ECC codes without external intervention. The controller continuously monitors data integrity and performs correction operations transparently, reducing the need for external error handling mechanisms and simplifying the overall system architecture.
3Reliability
If redundancy memory cells are used to replace defective cells, then yield enhancement is achieved, but repair capacity is limited
Solution Approach 1:
The patent uses parameter changes in ECC code generation and verification to enhance defect tolerance. By adjusting ECC code strength, parity bit configurations, or verification thresholds based on detected defect patterns, the system can adaptively handle various types and quantities of defective cells, providing flexible repair capacity beyond fixed redundancy schemes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability of ECC code operations, reducing errors and improving the overall accuracy of data storage and retrieval in resistive memory devices, thereby increasing the yield and reliability of the memory devices.
Implementation Method 1
resistive memory devices... materials having variable resistance such as transition-metal oxides... resistance thereof is variable depending on magnitude and/or direction of applied voltage and/or current
Implementation Method 2
the resistance can be maintained (that is, non-volatility) even though the applied voltage and/or current is intercepted and thus refresh operation is not required
Data Source
AI summary
To control operations of a resistive memory device, an input-output operation of an error check and correction (ECC) code is separated from an input-output operation of data. A condition of the input-output operation of the ECC code is determined stricter than a condition of the input-output operation of the data. reliability of the input-output operation of the ECC code may be enhanced, thereby reducing errors due to defect memory cells, noise, etc.