Resistive Memory Control Circuit for Endurance Optimization
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Solution Overview
Problem
Resistive memory devices face increased deterioration and reduced endurance due to the use of high reset voltages to achieve an obvious sense window, which compromises data discriminability and memory performance.
Innovation Solution
A resistive memory system comprising a control circuit, verification circuit, and storage circuits with flag bits that perform specific reset operations based on flag states to manage voltage application, distinguishing between normal and deteriorating memory cells to optimize reset operations and reduce deterioration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If larger reset voltage is applied to obtain an obvious sense window, then data discriminability is improved, but deterioration speed increases and endurance is reduced
Solution Approach 1:
The patent applies different reset voltages to different cell groups based on their operational status. Healthy cell groups receive standard reset voltage, while deteriorating cell groups receive reduced reset voltage. This local differentiation maintains data discriminability in healthy cells while protecting deteriorating cells from further stress, thereby resolving the contradiction between measurement precision and reliability.
Solution Approach 2:
The patent implements a feedback mechanism where the control circuit monitors the operational status of cell groups and dynamically adjusts reset voltage accordingly. The verification circuit provides feedback on cell group health, enabling the control circuit to switch between standard and reduced reset voltage modes. This closed-loop control ensures that high reset voltages are only applied when necessary, preventing unnecessary deterioration while maintaining data discriminability.
2Measurement precision
If continuous larger reset voltage is applied, then obvious sense window is maintained, but deterioration speed of resistive memory increases
Solution Approach 1:
The patent dynamically adjusts the reset voltage based on real-time monitoring of cell group status. The control circuit transitions between different voltage levels (standard and reduced) depending on whether the cell group is operating normally or showing signs of deterioration. This dynamic adaptation allows the system to maintain sense window clarity when needed while minimizing voltage stress during normal operation, thereby extending storage time.
Solution Approach 2:
The patent applies partial action by using reduced reset voltage for cell groups that are deteriorating but still functional. Instead of completely stopping reset operations, the system applies a mitigated version (reduced voltage) that maintains sufficient sense window while significantly lowering deterioration speed. This partial approach balances the need for data discriminability with the need to extend storage duration.
Data Source
AI summary
A resistive memory including a first storage circuit, a verification circuit, a second storage circuit and a control circuit is provided. The first storage circuit includes various cell groups. Each of the cell groups includes at least one memory cell. The verification circuit is coupled to the first storage circuit to verify whether a specific operation performed on at least one of the memory cells was successful. The second storage circuit includes various flag bits. Each of the flag bits corresponds to a cell group. In a reset period, the control circuit is configured to perform a first reset operation or a second reset operation on a first memory cell of a specific cell group among the cell groups according to a specific flag bit corresponding to the specific cell group.