Resistive Memory Erase Indicator for Stabilization Timing
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Solution Overview
Problem
Resistive memory devices, such as PRAM, RRAM, and MRAM, face challenges in accurately reading data due to the time required for phase change materials to stabilize in set or reset states, leading to potential incorrect readings if data is accessed before stabilization.
Innovation Solution
A method is introduced to operate resistive memory devices by using an erase indicator to manage the logic states of memory cells, allowing for controlled erasure and programming operations, including a flash-compatible mode and a non-compatible mode, to optimize data writing and reading processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data is read before phase change materials stabilize in set or reset states, then reading speed is improved, but measurement precision deteriorates due to potential incorrect readings
Solution Approach 1:
The patent introduces an erase indicator that is set in advance to indicate whether memory cells have been erased. This preliminary indication allows the reading operation to proceed without waiting for full stabilization of phase change materials, as the erase indicator provides advance information about the data state. The indicator is prepared beforehand to guide the reading process, enabling earlier data access while maintaining accuracy through informed reading operations.
2Adaptability or versatility
If flash-compatible program operation is used, then adaptability is improved for compatibility with existing systems, but productivity deteriorates due to longer programming time
Solution Approach 1:
The patent implements a dynamic operation mode selection mechanism that allows the resistive memory device to switch between flash-compatible mode and normal mode. The controller can dynamically choose the appropriate programming mode based on the specific application requirements. In flash-compatible mode, the device follows traditional erase-then-program sequences for compatibility. In normal mode, it can perform optimized programming operations that leverage the inherent characteristics of resistive memory, achieving faster programming speeds when compatibility is not required.
3Productivity
If normal program operation is used, then productivity is improved with faster programming, but adaptability deteriorates reducing compatibility with flash memory systems
Solution Approach 1:
The patent designs the resistive memory device with multi-functional capability to serve both flash memory compatibility requirements and high-performance applications. The device incorporates dual programming modes: flash-compatible mode that emulates traditional flash memory operations for system compatibility, and normal mode that optimizes for speed using resistive memory characteristics. This universal design allows the same hardware to fulfill different functional requirements, making it adaptable to various system architectures and application scenarios.
Data Source
AI summary
In one embodiment, the semiconductor device includes a non-volatile memory cell array, a write circuit configured to write to the non-volatile memory cell array, and a control circuit. The control circuit is configured to store at least one erase indicator. The erase indicator is associated with at least a portion of the non-volatile memory cell array and indicates a logic state. The control circuit is configured to control the write circuit to write the logic state indicated by the erase indicator in the non-volatile memory cell array during an erase operation of the associated portion of the non-volatile memory cell array.