Resistive Switching Memory Etch Sequence for Process Uniformity
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Solution Overview
Problem
Current semiconductor fabrication processes for resistive memory structures exhibit variations that lead to performance inconsistencies and increased overhead costs due to variations in semiconductor wafers and dies, resulting in reduced yield and potential detrimental impacts on memory performance over time.
Innovation Solution
The development of methods for fabricating resistive switching memory devices involves a two-step or three-step etch process, including the deposition of metal layers, switching matrices, and dielectric materials, with specific etching gases and techniques to form non-volatile and volatile resistive memory devices, as well as the use of nitrogen-rich metal layers and protective spacers to minimize process variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional single-step etching processes are used, then fabrication is simpler and faster, but process variations increase leading to performance inconsistencies
Solution Approach 1:
The etching process is divided into multiple sequential steps (e.g., first etch, second etch, third etch) with different selectivity ratios. Each step targets specific layers with controlled removal rates, allowing precise thickness control for each material layer while maintaining overall process uniformity across wafers and dies.
Solution Approach 2:
Different etching parameters (gas composition, power, pressure, temperature) are used in each etching step to achieve different selectivity ratios. By changing process parameters between steps, the method achieves varying removal rates for different materials, enabling precise control of layer thicknesses and reducing variability.
2Manufacturing precision
If process variations are minimized through multiple etching steps, then manufacturing precision improves, but fabrication complexity increases
Solution Approach 1:
The multi-step etching process uses a unified approach where each step follows the same basic procedure (deposit mask, etch with specific selectivity, remove mask) but with varying parameters. This modular, multi-functional process can be applied to different material combinations and device structures, reducing overall process complexity through standardization.
Solution Approach 2:
Each etching step is optimized with specific selectivity ratios tailored to the local requirements of different material layers. The first etch may target the switching matrix with high selectivity, while subsequent etches target donor layers or barrier layers with different selectivities, allowing precise local control without overwhelming global complexity.
3Manufacturing precision
If nitrogen-rich metal layers are used to minimize process variations, then manufacturing precision improves, but material composition complexity increases
Solution Approach 1:
The patent employs composite material structures including nitrogen-rich metal layers (e.g., tungsten nitride, titanium nitride) combined with oxide layers and dielectric materials. These composite structures provide controlled etching behavior and uniformity, with each material layer contributing specific properties that collectively reduce process variations.
Solution Approach 2:
The nitrogen content in metal layers is precisely controlled to achieve optimal etching selectivity and uniformity. By adjusting the nitrogen-to-metal ratio during deposition, the process achieves consistent results across wafers and dies, with the nitrogen-rich composition providing stable etching characteristics that reduce variability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
These methods enhance the uniformity and performance of resistive memory devices by reducing process variations, improving yield, and maintaining memory performance within acceptable specifications, thereby reducing overhead costs and ensuring reliable operation.
Implementation Method 1
etching the dielectric hard mask with a first etch and stopping the first etch on the electrically conductive first barrier material, the first etch comprising a plasma etch consisting of an etching gas selected from a first group consisting of: octafluorocyclobutane (C4F8), hexafluoro-2-butyne (C4F6), fluoroform (CHF3), carbon tetrafluoride (CF4), carbon monoxide (CO), oxygen (O2), dinitrogen (N2) and argon (Ar)
Implementation Method 2
The method can comprise depositing a metal layer overlying and in contact with a bottom electrode and with a dielectric material
Implementation Method 3
etching the electrically conductive barrier material, the optional barrier material layer, the donor material layer, the switching matrix and the metal layer with a second etch and stopping the second etch on the dielectric material, the second etch comprising a plasma etch consisting of an etching gas selected from a second group consisting of: chlorine (Cl2), boron trichloride (BCl3), hydrogen bromide (HBr), Ar, N2, helium (He), O2, CHF3, CF4, and sulfur hexafluoride (SF6)
Implementation Method 4
etching the electrically conductive barrier material, the optional barrier material layer, the donor material layer, the switching matrix and the metal layer with a second etch
Data Source
AI summary
Fabrication of resistive switching memory devices is herein provided. By way of example, a method for a two-step etch for fabricating a non-volatile resistive memory device is disclosed. In another example, a method for a three-step etch for fabricating a non-volatile resistive memory device is provided. Still other embodiments disclose a method for fabricating a non-volatile metal nitrogen/metal oxygen resistive switching memory device. Further embodiments disclose a method for fabricating a volatile resistive switching selector device. Processes for forming protective spacers in conjunction with fabricating a disclosed resistive memory device are also provided.