Resistive Memory Controller Fail Cell Inversion
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Solution Overview
Problem
Resistive memory devices face challenges in maintaining low write error rates and product reliability due to high failure rates in programming data, particularly when writing '0' to memory cells, which results in increased write errors and power consumption.
Innovation Solution
A memory device with a controller that detects fail cells by comparing written and read data, inverting the data when the failure rate exceeds a reference value, and reprogramming with the inverted data to reduce write errors and improve reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data is programmed into resistive memory cells, then data storage is achieved, but write error rate increases particularly when writing '0' to memory cells
Solution Approach 1:
The patent applies inversion by writing inverted data (opposite logic state) to memory cells that have high failure rates. Specifically, when a memory cell shows high failure rate for writing '0', the system writes '1' instead, and vice versa. This inversion principle directly addresses the contradiction by transforming the harmful writing operation into a beneficial one, reducing write errors while maintaining data storage functionality.
Solution Approach 2:
The patent changes the data parameter (logic state) based on the memory cell's performance characteristics. By detecting the failure rate of each memory cell and dynamically adjusting the data value to be written (inverting when failure rate is high), the system adapts the programming operation to the specific cell's state, thereby improving reliability without sacrificing storage capacity.
2Reliability
If multiple programming operations are performed to correct fail cells, then data accuracy improves, but power consumption increases
Solution Approach 1:
The patent performs preliminary detection of fail cells and determines the inversion strategy before actual data programming. By identifying memory cells with high failure rates in advance and pre-planning the inversion approach, the system avoids multiple retry programming operations, thereby reducing power consumption while ensuring data accuracy is achieved in the first write attempt.
Solution Approach 2:
The patent converts the harmful effect of high failure rates into a beneficial strategy by using the failure rate information itself to guide the inversion decision. The detected failures are not treated as errors to be corrected through repeated writes, but as useful information to determine which cells need inverted data, thereby eliminating the need for power-consuming retry operations.
3Reliability
If fail cells are detected and reprogrammed, then product reliability improves, but write operations increase causing more power consumption
Solution Approach 1:
The patent applies inversion as a single-step solution rather than a multi-step correction process. By inverting the data value before writing to fail cells, the system achieves reliable programming in one operation, avoiding multiple write cycles and thereby maintaining high productivity while improving product reliability.
Data Source
AI summary
A memory device includes a first nonvolatile memory including a resistive memory cell; and a controller. The controller may be configured to provide the first nonvolatile memory with a first data, a first program command, and a first address. The controller may be configured to receive a second data, which is a verify read from the resistive memory cell programmed with the first data, from the first nonvolatile memory in response to the first program command. The controller may be configured to compare the first data with the second data to detect a number of fail cells. When the number of detected fail cells is greater than a reference value, the controller may be configured to generate a third data obtained by inversing the first data, and provide the third data to the first nonvolatile memory. The first data may include an inversion flag bit.