Complementary Resistive Memory Read Circuit for Single Flip-Error Detection
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Solution Overview
Problem
Complementary Magnetic Tunneling Junction (MTJ) based memory bit-cells face retention errors due to uncertain read issues when one MTJ flips, leading to conflicting sensing modes and increased reading latency in existing solutions.
Innovation Solution
A dual sense amplifier architecture is introduced, where a second sense amplifier detects errors simultaneously with the first sense amplifier, enabling error location identification and using an errors-and-erasures decoding process to improve error correction, thereby reducing read latency and power consumption and eliminating silent corruption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a second read mode (Salvage Mode) is employed to identify confliction by reading the two MTJs separately, then retention error detection capability is improved, but reading latency increases
Solution Approach 1:
The patent applies preliminary action by performing error detection during the normal read operation itself. The sense amplifier simultaneously performs both data sensing and error detection functions in the same read cycle, rather than requiring a separate salvage read mode. This is achieved by configuring the sense amplifier to detect whether the read data matches the expected complementary state, thereby identifying retention errors without additional read latency.
Solution Approach 2:
The patent merges the error detection function with the normal read operation. The sense amplifier is designed to perform both data sensing and retention error detection in a single operation by comparing the read data with the expected complementary state. This consolidation eliminates the need for a separate salvage read mode, thereby maintaining fast read latency while improving reliability through simultaneous error detection.
2Reliability
If a second read mode (Salvage Mode) is employed to identify confliction, then retention error detection capability is improved, but device complexity increases
Solution Approach 1:
The sense amplifier is designed with multi-functionality to perform both normal data sensing and retention error detection within the same circuit and operation cycle. By making the sense amplifier universal in its function, the patent eliminates the need for separate salvage read logic, thereby improving reliability without increasing device complexity. The same hardware resources are utilized for dual purposes.
Solution Approach 2:
The patent combines the error detection logic with the existing read logic in the sense amplifier. Rather than adding a separate salvage read mode with its own complex logic, the error detection is integrated into the normal read path by comparing read data against expected complementary states. This merging approach improves reliability while keeping the device complexity manageable.
3Reliability
If traditional error correction is used without error location information, then error correction capability is limited, but system complexity remains low
Solution Approach 1:
The patent implements feedback by using the detected error location information to guide the error correction process. When a retention error is detected, the system identifies which specific MTJ cell contains the error and provides this location information to the correction logic. This feedback mechanism enables targeted correction of the erroneous cell, significantly improving error correction capability compared to blind error correction methods.
Solution Approach 2:
The patent performs preliminary error location identification during the read operation itself. By detecting and identifying the location of retention errors in advance, before the correction process begins, the system enables more efficient and effective error correction. This preliminary action provides valuable information that enhances the error correction capability without requiring overly complex decoding processes.
Data Source
AI summary
Described is an apparatus which comprises: a complementary resistive memory bit-cell; a first sense amplifier coupled to the complementary resistive memory bit-cell via access devices; a second sense amplifier coupled to the first sense amplifier and to the complementary resistive memory bit-cell via the access devices, wherein the second sense amplifier is operable to detect an error in the complementary resistive memory bit-cell.