Resistive Memory Device Forming Uniformity via Segmented Voltage
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Solution Overview
Problem
The forming process of resistive random-access memory devices is hindered by increased forming time and reduced uniformity due to IR drop and leakage currents, which affect the consistency and efficiency of the voltage application across memory cells.
Innovation Solution
The resistive memory device is designed with memory cells grouped into zones based on their connection length to the driver, with a specific forming order from farther to nearer positions, and distinct voltage values applied to each zone to minimize leakage and ensure uniform voltage distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the forming voltage is gradually increased to overcome IR drop and leakage currents, then the forming process can be completed, but the forming time increases and forming uniformity deteriorates
Solution Approach 1:
The patent divides the memory cell array into multiple zones based on connection length to the driver. Each zone is formed sequentially with optimized voltage parameters, avoiding the need to gradually increase voltage across all cells. This segmentation allows simultaneous formation of cells in the same zone with uniform voltage application, reducing total forming time while maintaining reliability.
Solution Approach 2:
The patent applies different forming voltage parameters to different zones based on their specific connection characteristics. Cells in zones with longer connection lengths receive higher forming voltages to compensate for IR drop, while cells in zones with shorter connection lengths receive lower forming voltages. This localized voltage optimization reduces leakage currents and improves forming uniformity without extending forming time.
2Reliability
If the forming voltage is gradually increased to overcome IR drop and leakage currents, then the forming process can be completed, but the forming uniformity deteriorates
Solution Approach 1:
The patent segments the memory cell array into multiple zones based on connection length to the driver. Each zone is formed sequentially with optimized voltage parameters, avoiding the need to gradually increase voltage across all cells. This segmentation allows simultaneous formation of cells in the same zone with uniform voltage application, reducing total forming time while maintaining reliability.
Solution Approach 2:
The patent applies different forming voltage parameters to different zones based on their specific connection characteristics. Cells in zones with longer connection lengths receive higher forming voltages to compensate for IR drop, while cells in zones with shorter connection lengths receive lower forming voltages. This localized voltage optimization reduces leakage currents and improves forming uniformity without extending forming time.
3Ease of manufacture
If memory cells are formed simultaneously with uniform voltage, then the process is simple, but IR drop and leakage currents cause non-uniform formation across cells with different connection lengths
Solution Approach 1:
The patent segments the memory cell array into multiple zones based on connection length to the driver. Each zone is formed sequentially with optimized voltage parameters, avoiding the need to gradually increase voltage across all cells. This segmentation allows simultaneous formation of cells in the same zone with uniform voltage application, reducing total forming time while maintaining reliability.
Solution Approach 2:
The patent applies different forming voltage parameters to different zones based on their specific connection characteristics. Cells in zones with longer connection lengths receive higher forming voltages to compensate for IR drop, while cells in zones with shorter connection lengths receive lower forming voltages. This localized voltage optimization reduces leakage currents and improves forming uniformity without extending forming time.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the forming time and uniformity of the resistive memory device by optimizing voltage application and reducing leakage currents, leading to more efficient and consistent state transitions between set and reset states.
Implementation Method 1
The driver is configured to provide a forming voltage to the first memory cells and the second memory cells through the bit lines and the source lines
Implementation Method 2
The forming voltage of the forming process may be gradually increased due to IR drop and leakage currents
Data Source
AI summary
A resistive memory device includes word lines, first memory cells, second memory cells, bit lines, source lines, and a driver. The driver provides a forming voltage to the first memory cells and the second memory cells through the bit lines and the source lines in a forming process. A first connection length along the bit lines and the source lines between the first memory cells and the driver is longer than a second connection length along the bit lines and the source lines between the second memory cells and the driver. The forming process is performed to the first memory cells before the forming process is performed to the second memory cells. A first value of the forming voltage provided to the first memory cells is less than a second value of the forming voltage provided to the second memory cells.