Integrated Resistive Memory With High-k Gate Dielectrics for RESET Voltage
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As technology nodes decrease, integrating resistive memory cells into individual integrated circuits (ICs) becomes challenging due to insufficient output voltages from semiconductor devices, which are necessary for operating the resistive memory cells, especially during RESET operations.
Innovation Solution
The method involves forming a first semiconductor device and a second semiconductor device with different output voltages on a semiconductor substrate. The second semiconductor device is electrically coupled to a resistive memory cell. By using a second gate dielectric structure with a higher dielectric constant than the first gate dielectric structure, the output voltage of the second semiconductor device is increased to ensure it can operate the resistive memory cell effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If technology nodes are decreased to improve integration density, then more devices can be integrated on a chip, but the output voltage from semiconductor devices becomes insufficient to operate resistive memory cells
Solution Approach 1:
The patent applies local quality by using different gate dielectric structures for different semiconductor devices on the same chip. Specifically, the memory region uses a first gate dielectric structure with higher dielectric constant to provide higher output voltage for memory operations, while the logic region uses a second gate dielectric structure with lower dielectric constant. This allows each region to have optimized electrical characteristics suited to its specific functional requirements, resolving the voltage insufficiency issue in high-density integrated circuits.
Solution Approach 2:
The patent changes the dielectric constant parameter of the gate dielectric material to resolve the voltage issue. By selecting gate dielectric materials with different dielectric constants for different regions, the patent adjusts the electrical parameters of semiconductor devices locally. The first gate dielectric structure has a higher dielectric constant than the second, which directly increases the output voltage capability of memory devices without affecting logic device performance.
2Ease of manufacture
If a single gate dielectric structure is used for all semiconductor devices, then manufacturing is simplified, but memory devices cannot receive sufficient voltage for RESET operations
Solution Approach 1:
The patent implements local quality by differentiating gate dielectric structures between memory and logic regions. The memory region employs a first gate dielectric structure with higher dielectric constant specifically tailored to provide sufficient voltage for memory SET and RESET operations, while the logic region uses a second gate dielectric structure with lower dielectric constant. This regional differentiation ensures memory operation reliability without compromising manufacturing feasibility, as both structures can be formed using similar fabrication processes.
3Power
If gate dielectric with higher dielectric constant is used in memory region, then sufficient voltage is provided for memory operations, but device complexity increases due to different gate dielectric structures
Solution Approach 1:
The patent applies segmentation by dividing the semiconductor chip into distinct memory and logic regions, each with its own optimized gate dielectric structure. The memory region is segmented to use a first gate dielectric structure with higher dielectric constant for sufficient voltage output, while the logic region uses a second gate dielectric structure. This segmentation allows voltage optimization for memory operations while containing the increased complexity to specific regions rather than the entire chip.
Solution Approach 2:
The patent changes the dielectric constant parameter of gate dielectric materials to achieve sufficient output voltage for memory operations. By selecting appropriate dielectric materials with different constants for different regions, the patent optimizes electrical parameters locally. The first gate dielectric structure has a higher dielectric constant than the second, enabling memory devices to achieve the necessary voltage levels for reliable SET and RESET operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the successful integration of resistive memory cells into individual ICs as technology nodes decrease, ensuring that the resistive memory cells receive the necessary voltage for proper operation.
Implementation Method 1
By using a second gate dielectric structure with a higher dielectric constant than the first gate dielectric structure, the output voltage of the second semiconductor device is increased
Data Source
AI summary
In some embodiments, a method for forming an integrated chip (IC) is provided. The method incudes forming an interlayer dielectric (ILD) layer over a substrate. A first opening is formed in the ILD layer and in a first region of the IC. A second opening is formed in the ILD layer and in a second region of the IC. A first high-k dielectric layer is formed lining both the first and second openings. A second dielectric layer is formed on the first high-k dielectric layer and lining the first high-k dielectric layer in both the first and second regions. The second high-k dielectric layer is removed from the first region. A conductive layer is formed over both the first and second high-k dielectric layers, where the conductive layer contacts the first high-k dielectric layer in the first region and contacts the second high-k dielectric in the second region.