Resistive-Memory Neural Network Circuits for In-Memory Computing
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Solution Overview
Problem
The frequent movement of large amounts of data between a processor and a memory in von Neumann computer architecture causes long delays and high power consumption, particularly in machine learning applications, which can be mitigated by using neuromorphic architectures that perform operations directly at the memory device and store synaptic weights.
Innovation Solution
A neural network circuit utilizing resistive memory elements with variable resistance values to simulate synaptic connections, incorporating synaptic and reference memory cells, and an output circuit to generate signals based on resistance values and input signals, enabling efficient data processing and reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If von Neumann computer architecture is used for machine learning operations, then data can be processed using general-purpose processors, but frequent data movement between processor and memory causes long delays and high power consumption
Solution Approach 1:
The patent merges the processor and memory into a single integrated neural network circuit where synaptic weights are stored in resistive memory elements directly within the computing unit. This eliminates the separate processor-memory architecture of von Neumann systems, allowing computations to be performed directly on stored data without data movement, thus reducing power consumption while maintaining processing capability
Solution Approach 2:
The patent introduces resistive memory elements as intermediary components that serve dual functions: storing synaptic weights and performing computational operations. These memory elements act as mediators between data storage and processing, enabling in-memory computing where weights are stored and used for computations simultaneously, eliminating the need for frequent data transfer between separate processor and memory units
2Productivity
If data is frequently moved between processor and memory in von Neumann architecture, then computations can be performed, but this causes long delays and limits chip performance
Solution Approach 1:
The patent combines storage and computation functions into a single integrated circuit where resistive memory elements store synaptic weights and simultaneously participate in computational operations. This merging eliminates the sequential nature of von Neumann architecture where data must be moved between separate processor and memory units, thereby removing data movement delays and improving computational throughput
Solution Approach 2:
The patent segments the neural network circuit into multiple parallel processing units, each with its own resistive memory elements for storing synaptic weights. This segmentation allows simultaneous execution of multiple computations across different weight sets, increasing overall productivity while eliminating the need for data movement between centralized processor and memory
3Adaptability or versatility
If large amounts of data are moved between processor and memory, then machine learning operations can be executed, but this results in high power consumption
Solution Approach 1:
The patent merges data storage and data processing into a single integrated neural network circuit where resistive memory elements store synaptic weights and directly participate in computational operations. This eliminates the energy-consuming data movement between separate processor and memory units, significantly reducing energy loss while maintaining full machine learning operation capability
Solution Approach 2:
The resistive memory elements serve themselves by simultaneously storing synaptic weights and performing computational operations. The memory structure inherently supports the computation function through its electrical properties, eliminating the need for separate processing units that would require energy-intensive data retrieval and transfer, thus reducing energy loss
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces data movement and power consumption by performing operations directly at the memory device, enhancing chip performance and enabling efficient implementation of machine learning tasks.
Implementation Method 1
a resistive memory element, which is disposed along an output line and which is configured to vary between having a first resistance value and a second resistance value as a resistance value
Implementation Method 2
the synaptic memory cell is configured to generate a column signal, based on the resistance value of the resistive memory element and an input signal received via an input line
Implementation Method 3
the reference memory cell is configured to generate a reference signal, based on the resistance value of the reference memory element and the input signal
Implementation Method 4
an output circuit configured to generate an output signal for the output line based on the column signal and the reference signal
Data Source
AI summary
A neural network method and device are included, A neural network circuit includes a synaptic memory cell including a resistive memory element, which is disposed along an output line and which can have a first resistance value and a second resistance value as a resistance value, the synaptic memory cell generates a column signal, based on the resistance value of the resistive memory element and an input signal received via an input line, a reference memory cell including a reference memory element, which is disposed along a reference line and which has a resistance value that is a ratio of the first and second resistance values, the reference memory cell generates a reference signal, based on the resistance value of the reference memory element and the input signal, and an output circuit generates an output signal for the output line based on the column signal and the reference signal.