Resistive Memory Inhibit Voltage Leakage Control
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Solution Overview
Problem
Resistive memory devices face challenges in reducing leakage current in dummy cells connected to dummy lines, which affects the reliability and efficiency of memory operations.
Innovation Solution
The implementation of a method to adjust the inhibit voltage applied to dummy lines based on the detected address and position of selected signal lines, using a plurality of inhibit voltages to reduce leakage current in resistive memory devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If a fixed inhibit voltage is applied to dummy lines, then the circuit design is simple, but leakage current in dummy cells cannot be effectively reduced
Solution Approach 1:
The patent applies dynamics by transitioning from a fixed inhibit voltage to a dynamically adjustable inhibit voltage that varies based on the selected bit line position. The controller determines the inhibit voltage level according to the address of the selected bit line, enabling adaptive leakage current reduction in dummy cells while maintaining manageable circuit complexity through systematic voltage selection.
Solution Approach 2:
The patent implements parameter changes by varying the inhibit voltage parameter applied to dummy lines based on the selected bit line position. Different inhibit voltage levels (first, second, third inhibit voltages) are applied to different dummy lines corresponding to different bit line positions, optimizing leakage current reduction through parameter adaptation.
2Reliability
If multiple inhibit voltage levels are applied to different dummy lines, then leakage current reduction is improved, but the control circuit complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the dummy lines into multiple groups, with each group associated with specific bit line positions and receiving appropriate inhibit voltage levels. The controller segments the voltage control task by detecting the selected bit line address and selecting the corresponding inhibit voltage from multiple available levels, thereby improving reliability while keeping the control logic systematic and manageable.
Solution Approach 2:
The patent implements feedback by using the address detection result of the selected bit line to determine the appropriate inhibit voltage level for dummy lines. The controller receives feedback from the address detector about which bit line is selected and accordingly selects the appropriate inhibit voltage, creating a closed-loop control system that enhances reliability without excessive complexity.
Data Source
AI summary
A method of operating a resistive memory device and a resistive memory system including a resistive memory device is for a resistive memory device including a plurality of bit lines and at least one dummy bit line. The method of operating the resistive memory device includes detecting a first address accompanying a first command, generating a plurality of inhibit voltages for biasing non-selected lines, and providing to a first dummy bit line a first inhibit voltage selected from among the plurality of inhibit voltages based on a result of detecting the first address.