Resistive Memory Leakage Current Reduction via Block Voltage Segmentation
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Solution Overview
Problem
Resistive memory devices face challenges in reducing leakage current in unselected memory cells during writing or reading operations, which affects the integrity and efficiency of memory operations.
Innovation Solution
The method involves determining the operating current flowing through selected signal lines and dividing the memory cell array into blocks based on this current, applying inhibit voltages with varying voltage levels to unselected signal lines to minimize leakage current. This approach adjusts the voltage differences between inhibit voltages based on the operating current, ensuring constant voltage levels across memory cells and reducing leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a single inhibit voltage level is applied to all unselected second signal lines, then the device complexity is reduced, but the leakage current in unselected memory cells cannot be sufficiently reduced due to varying voltage drops along different signal lines
Solution Approach 1:
The memory cell array is divided into multiple blocks along the first signal line direction, and different inhibit voltage levels are applied to unselected second signal lines in different blocks. This segmentation allows the system to address the varying voltage drops in different regions by providing region-specific inhibit voltages, thereby reducing leakage current more effectively while managing device complexity through structured division.
Solution Approach 2:
Different inhibit voltage levels are applied to different blocks of the memory cell array based on their specific voltage drop characteristics. Blocks experiencing greater voltage drops receive higher inhibit voltages, while blocks with smaller voltage drops receive lower inhibit voltages. This local quality approach ensures that each region receives the appropriate voltage level to minimize leakage current, rather than applying a uniform voltage across the entire array.
2Object-affected harmful factors
If the memory cell array is divided into many blocks with different inhibit voltages, then the leakage current is reduced, but the device complexity increases due to the need to manage multiple voltage levels
Solution Approach 1:
The number of blocks and the specific inhibit voltage levels applied to each block are dynamically determined based on the operating current value. The control logic analyzes the operating current and adjusts the block division and voltage assignment accordingly, allowing the system to optimize between leakage reduction and complexity management based on actual operating conditions rather than using a fixed configuration.
Solution Approach 2:
The inhibit voltage levels and block configuration are adjusted as parameters based on the operating current. When the operating current changes, the system modifies the number of blocks and the voltage levels applied to each block, enabling adaptive optimization of leakage current reduction while managing device complexity through parameter-based control rather than structural redesign.
3Speed
If the operating current is increased to improve writing speed, then the writing speed increases, but the leakage current in unselected memory cells increases due to larger voltage drops
Solution Approach 1:
The system applies inhibit voltages to unselected second signal lines in advance before writing operations to counteract the potential leakage current caused by upcoming high operating currents. By pre-applying appropriate inhibit voltages based on the selected first signal line's operating current, the system prepares the unselected memory cells to resist leakage current, enabling high-speed writing without compromising data integrity in unselected cells.
Solution Approach 2:
The control logic determines the operating current value and uses this information to dynamically adjust the block division and inhibit voltage levels. This feedback mechanism ensures that when higher operating currents are used for faster writing, the system automatically increases the inhibit voltages in affected blocks to compensate for the increased leakage current, thereby maintaining both speed and reliability.
Data Source
AI summary
A method of operating a memory device includes determining a value of an operating current flowing through a selected first signal line, to which a selection voltage is applied, from among a plurality of first signal lines; dividing an array of memory cells into n blocks, n being an integer greater than 1, based on the value of the operating current; and applying inhibit voltages having different voltage levels corresponding to the n blocks to unselected ones of second signal lines included in the n blocks. Each of the unselected second signal lines is a pathway through which leakage current may potentially flow due to the operating current flowing through the selected first signal line and a memory cell addressed by the unselected second signal line and the selected first signal line.