Resistive Memory Leakage Current Control via Local Voltage Segmentation
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Solution Overview
Problem
Next-generation memory devices face challenges in minimizing leakage current during writing and reading operations, which affects their performance and efficiency.
Innovation Solution
A method for operating resistive memory devices involves applying specific voltage levels to unselected signal lines in relation to selected lines, with voltage differences determined based on the operation mode, to minimize leakage current. This includes applying a first voltage to unselected signal lines not adjacent to the selected signal line, a second voltage to adjacent unselected signal lines, and a third voltage to the selected signal line, while floating the unselected signal lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single voltage level is applied to all unselected signal lines, then the control is simple, but leakage current cannot be effectively minimized in adjacent unselected memory cells
Solution Approach 1:
The patent applies different voltage levels to different groups of unselected signal lines based on their proximity to selected lines. Specifically, unselected signal lines adjacent to selected lines receive a first voltage level, while unselected signal lines not adjacent to selected lines receive a second voltage level. This local differentiation allows optimized leakage current control in each region without requiring a completely complex control system.
Solution Approach 2:
The patent segments the unselected signal lines into two distinct groups: those adjacent to selected lines and those not adjacent to selected lines. This segmentation enables independent voltage control for each group, allowing the system to minimize leakage current in adjacent cells while maintaining simpler control for non-adjacent cells.
2Reliability
If multiple voltage levels are applied to different unselected signal lines, then leakage current is minimized, but the control mechanism becomes more complex
Solution Approach 1:
The patent implements local quality by applying different voltage levels to different spatial regions of unselected signal lines. Adjacent unselected lines receive one voltage level optimized for minimizing leakage current, while non-adjacent unselected lines receive another voltage level. This localized optimization improves operational integrity without requiring uniform complex control across the entire array.
Solution Approach 2:
The patent applies voltage levels to unselected signal lines before activating the selected memory cell. By pre-applying the appropriate voltage levels to adjacent and non-adjacent unselected lines in a predetermined sequence, the system prepares the memory array to minimize leakage current during the subsequent read or write operation, improving operational integrity proactively.
3Stability of the object's composition
If unselected signal lines are floated after voltage application, then voltage stability is improved, but the timing control becomes more precise and complex
Solution Approach 1:
The patent floats the unselected signal lines after applying the appropriate voltage levels in a predetermined timing sequence. By completing the voltage application to both adjacent and non-adjacent unselected lines before floating them, the system ensures voltage stability is achieved without introducing excessive timing complexity. The floating operation is performed as a preliminary step before the main memory operation.
Solution Approach 2:
The patent employs periodic timing control where voltage application and floating operations are executed in repeated cycles for different signal line groups. The timing sequence follows a periodic pattern: apply voltage to non-adjacent lines, apply voltage to adjacent lines, then float all unselected lines. This periodic action allows voltage stability to be maintained while using predictable timing that reduces overall complexity.
Data Source
AI summary
A resistive memory device including multiple resistive memory cells arranged in regions where first signal lines and second signal lines cross each other, and a method of operating the resistive memory device, are provided. The method includes applying a first voltage to a first line, from among unselected first signal lines connected to unselected memory cells, that is not adjacent to a selected first signal line connected to a selected memory cell from among the multiple memory cells; applying a second voltage that is lower than the first voltage to a second line, from among the unselected first signal lines, that is adjacent to the selected first signal line; floating the unselected first signal lines; and applying a third voltage that is higher than the first voltage to the selected first signal line.