Resistive Memory LUT Circuit With Separated Read Path
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Solution Overview
Problem
Conventional lookup table circuits in programmable logic devices suffer from a small read margin due to voltage drop across multiple series-connected transistors in the selection circuit and mode selector, which decreases read speed.
Innovation Solution
A lookup table circuit design where the selection circuit is separated from the read-current path, using a memory cell array with resistive memory elements and a single-ended sense amplifier, allowing direct voltage detection without passing through the selection circuit, thereby enhancing the read margin.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the selection circuit is connected in series with the read circuit path, then the circuit structure is compact and area is reduced, but the read margin decreases due to voltage drop across multiple series-connected transistors
Solution Approach 1:
The patent divides the circuit into separate functional blocks: the selection circuit (4a) and the read circuit (3) with sense amplifiers (3a, 3b). By segmenting these circuits and connecting them in parallel rather than series, the voltage drop affecting read margin is eliminated while maintaining compact overall layout through shared memory cell array connectivity.
Solution Approach 2:
The patent introduces a mode selector (2a) as an intermediary component that manages the connection between the selection circuit and read circuit. This mediator enables flexible switching between different operational modes, allowing the selection circuit to control memory cell access without being in the direct read path, thus preserving read margin while maintaining selection functionality.
2Adaptability or versatility
If multiple series-connected transistors are used in the selection circuit for multi-input LUT, then the selection functionality is achieved, but the read speed decreases due to accumulated voltage drop
Solution Approach 1:
The patent segments the 6-input LUT functionality into a combination of selection circuit operations and read circuit operations. The selection circuit uses series-connected transistors for address decoding and cell selection, while the read circuit with sense amplifiers performs the actual data retrieval in parallel, eliminating the speed penalty from series transistor traversal during read operations.
Solution Approach 2:
The patent transitions from a single-series-path architecture to a two-dimensional architecture where the selection circuit operates in one dimension (address decoding) and the read circuit operates in another dimension (data sensing). This dimensional separation allows multi-input LUT functionality to be achieved without compromising read speed, as the sense amplifiers can detect voltage differences simultaneously across multiple selected cells.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The separation of the selection circuit from the read path improves the read margin and reduces circuit area, enabling faster data retrieval even with small resistance differences, and reduces delay time.
Implementation Method 1
A nonvolatile FPGA employs a configuration of a logic device using a resistive memory element, for example
Implementation Method 2
it is necessary to pass through multiple series-connected transistors in the selection circuit 4a, which results in a small read margin due to voltage drop
Data Source
AI summary
A lookup table circuit constituting a programmable logic device includes: a memory cell array including a plurality of memory cells, each having a resistive memory element; a selection circuit connected to the memory cell array and configured to output, to the memory cell array, a single cell-select signal or two or more cell-select signals for selecting a single memory cell or two or more memory cells among the plurality of memory cells, based on input of a plurality of logic signals; and a read circuit connected to the memory cell array and configured to read data from the single memory cell or the two or more memory cells selected by the single cell-select signal or the two or more cell-select signals, among the plurality of memory cells. The selection circuit is separated from a path along which the read circuit is configured to read data from the memory cell array.