Resistive Memory Cells for Multilevel Resistance-State Control
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Solution Overview
Problem
Existing resistive memory devices face challenges in efficiently programming and storing multiple bits in a single memory cell, particularly in managing the resistance states to achieve multi-level or triple-level cell schemes effectively.
Innovation Solution
The resistive memory device includes a data storage layer made of bipolar or unipolar resistive materials, with controlled application of voltages to word lines and bit lines to manage resistance states, allowing for programming and erasing operations, and a method that involves applying specific voltage levels to select and unselect word lines and bit lines to achieve various resistance states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a single memory cell stores multiple bits by managing multiple resistance states, then data storage capacity increases, but the complexity of controlling resistance states increases
Solution Approach 1:
The patent segments the control of resistance states by dividing word lines into selected and unselected groups, and bit lines into selected and unselected groups. This segmentation allows independent control of voltage application to different memory cells, enabling multi-bit storage per cell while managing the complexity through systematic voltage distribution across segmented line groups.
Solution Approach 2:
The patent employs dynamic voltage control where turn-on voltages and turn-off voltages are selectively applied to different word lines and bit lines based on the desired program target state. The voltage levels are dynamically adjusted during programming operations to transition memory cells between different resistance states (R1, R2, R3), enabling flexible multi-level cell operation.
2Manufacturing precision
If turn-on voltage levels are controlled depending on program target state to achieve multi-level cell schemes, then manufacturing precision of resistance states improves, but the complexity of voltage control increases
Solution Approach 1:
The patent changes the parameter of voltage level by applying different turn-on voltages (first turn-on voltage, second turn-on voltage, third turn-on voltage) corresponding to different program target states (first program state, second program state, third program state). This parameter change enables precise control of resistance states to achieve multi-level cell schemes with distinct resistance levels (R1, R2, R3) for reliable data storage.
Solution Approach 2:
The voltage generator controls the level of turn-on voltage applied to unselected word lines based on feedback regarding the program target state of selected resistive memory cells. This feedback mechanism ensures that the appropriate voltage level is applied to achieve the desired resistance state, improving manufacturing precision while managing control complexity through automated voltage selection.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the resistive memory device to store multiple bits in a single cell, supporting multi-level and triple-level cell schemes by effectively controlling resistance states, enhancing data storage capacity and efficiency.
Implementation Method 1
The data storage layer may be programmed or erased through resistance varying with a voltage that is applied to the electrodes
Data Source
AI summary
Provided herein may be a resistive memory device and a method of operating the resistive memory device. The resistive memory device may include strings coupled between one or more source lines and one or more bit lines, each string including a set of one or more resistive memory cells, one or more word lines respectively coupled to the set of one or more resistive memory cells; and a voltage generator configured to control a level of a turn-on voltage to be applied to one or more unselected word lines among the one or more word lines depending on a program target state of a subset of resistive memory cells including one or more resistive memory cells selected from among the set of one or more resistive memory cells.