Multi-layer Resistive Memory Device with Offset Word Lines
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Solution Overview
Problem
Existing semiconductor memory devices with a cross-point type structure face challenges in minimizing heat disturbance during write operations, leading to potential data reliability issues due to heat propagation affecting adjacent memory cells.
Innovation Solution
The semiconductor memory device employs a configuration where word lines and bit lines are shifted in the in-plane direction in each wiring layer, dispersing heat generated during write operations, thereby reducing the impact on unselected memory cells and enhancing data reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If word lines and bit lines are arranged in a cross-point structure with overlapping centers, then memory cell density is improved, but heat disturbance propagates to adjacent memory cells causing data reliability issues
Solution Approach 1:
The patent applies asymmetry by intentionally offsetting the centers of word lines and bit lines so they do not fully overlap. This asymmetric arrangement creates spatial separation that disperses heat generation away from adjacent memory cells, reducing heat disturbance while maintaining high memory cell density through the cross-point structure
Solution Approach 2:
The patent utilizes the planar dimension by shifting word lines and bit lines in the in-plane direction rather than maintaining vertical alignment. This dimensional adjustment allows the memory cells to remain densely packed in the cross-point configuration while introducing horizontal separation that effectively reduces heat propagation to neighboring cells
2Reliability
If the interval between selected and unselected memory cells is increased to reduce heat influence, then data reliability is improved, but memory cell density decreases
Solution Approach 1:
The asymmetric offset arrangement allows memory cells to be positioned closer together in terms of center-to-center distance while ensuring that the active regions of selected and unselected cells do not overlap significantly. This creates effective heat isolation without sacrificing nominal memory cell density
Solution Approach 2:
The patent creates different spatial relationships for different memory cell pairs - selected memory cells have sufficient separation for heat isolation, while unselected adjacent cells maintain close proximity for high density. The offset configuration selectively applies spacing where heat propagation occurs during write operations
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively suppresses heat propagation to unselected memory cells, improving the reliability of data storage by increasing the interval between selected and unselected memory cells, thus minimizing the influence of heat-induced disturbances.
Implementation Method 1
a fifth conductor includes a variable resistance unit and is between the first and second conductors in the third direction
Data Source
AI summary
A semiconductor memory device includes a first conductor extending in a first direction and a second conductor extending in a second direction and disposed above the first conductor in a third direction. Third and fourth conductors extend in the first direction and adjacent to each other in the second direction. The third and fourth conductors are above the second conductor. A fifth conductor includes a variable resistance unit and is between the first and second conductors. A sixth conductor includes a variable resistance unit and is between the third and second conductors. A seventh conductor includes a variable resistance unit and is between the fourth and second conductors. A center point of the fifth conductor along a width of the fifth conductor is does not fully overlap with either of the sixth or seventh conductors along the third direction.