Resistive-Memory Neuromorphic Circuit for Parallel Multiply-Accumulate
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional microprocessor technology is limited by chronological operation execution, leading to inefficiencies in computational performance, power consumption, and physical size, making it unsuitable for applications requiring significant computational efficiency like image recognition, and large-scale neuromorphic computing networks are too space and power intensive for industries such as biomedical, military, and mobile devices.
Innovation Solution
Analog neuromorphic circuits utilizing resistive memories are implemented with parallel multiplication and addition operations, leveraging resistive memories positioned at wire grid intersections to execute multiple operations simultaneously, reducing power consumption and physical size while maintaining high computational efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional microprocessor technology is used with chronological operation execution, then device complexity is reduced and ease of operation is maintained, but computational efficiency deteriorates and power consumption increases
Solution Approach 1:
The patent replaces conventional digital microprocessor architecture with an analog neuromorphic computing system that mimics biological neural networks. This substitution enables parallel processing of computational operations, fundamentally changing the mechanical/electronic system architecture from sequential to parallel operation, thereby achieving exponential improvements in computational efficiency while reducing power consumption by 1,000 to 1,000,000 times
Solution Approach 2:
The invention transitions from one-dimensional sequential processing in conventional microprocessors to multi-dimensional parallel processing in the analog neuromorphic circuit. By organizing computational elements in a two-dimensional crossbar array architecture, the system enables simultaneous execution of multiple operations across different spatial dimensions, resolving the contradiction between computational efficiency and power consumption
2Productivity
If conventional neuromorphic computing networks are implemented in large scale computer clusters, then computational efficiency is improved, but physical space requirements increase and power consumption increases
Solution Approach 1:
The patent merges multiple computational functions into a single integrated analog neuromorphic circuit chip. By combining multiplication, addition, and neural network processing operations into one unified device using resistive memory crossbar arrays, the system achieves high computational efficiency without requiring large-scale computer clusters, thereby dramatically reducing physical space requirements
Solution Approach 2:
The analog neuromorphic circuit implements universal computational capabilities that can perform multiple operations simultaneously - including matrix multiplication, vector addition, and neural network inference - within a single device. This multi-functionality eliminates the need for separate specialized hardware components, reducing the overall physical footprint while maintaining exponential computational efficiency
3Productivity
If conventional neuromorphic computing networks are implemented in large scale computer clusters, then computational efficiency is improved, but power consumption increases
Solution Approach 1:
The patent replaces energy-intensive digital computation with low-power analog computation in the neuromorphic circuit. By using analog voltage and current signals to represent and process information, the system achieves exponential computational efficiency while consuming 1,000 to 1,000,000 times less power than conventional digital microprocessors, resolving the contradiction between productivity and energy consumption
4Speed
If chronological operation execution is used in conventional microprocessors, then device complexity is reduced, but speed of operation deteriorates
Solution Approach 1:
The patent implements a two-dimensional crossbar array architecture where computational operations occur simultaneously across multiple spatial dimensions. This dimensional expansion allows the system to execute numerous operations in parallel rather than sequentially, achieving exponential speedup while the modular crossbar structure keeps the circuit architecture manageable and scalable
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves exponential increases in computational efficiency and reduces power requirements by 1,000 to 1,000,000 times compared to traditional microprocessors, enabling applications like image recognition and learning algorithms in compact form factors suitable for limited space and power resources.
Implementation Method 1
The plurality of resistive memories is configured to provide a resistance to each input voltage applied to each of the inputs so that each input voltage is multiplied in parallel by the corresponding resistance of each corresponding resistive memory to generate a corresponding current for each input voltage
Implementation Method 2
resistive memories...configured to provide a resistance to each input voltage...Multiplying each input voltage with each corresponding resistance is executed simultaneously with adding each corresponding current
Data Source
AI summary
An analog neuromorphic circuit is disclosed, having input voltages applied to a plurality of inputs of the analog neuromorphic circuit. The circuit also includes a plurality of resistive memories that provide a resistance to each input voltage applied to each of the inputs so that each input voltage is multiplied in parallel by the corresponding resistance of each corresponding resistive memory to generate a corresponding current for each input voltage and each corresponding current is added in parallel. The circuit also includes at least one output signal that is generated from each of the input voltages multiplied in parallel with each of the corresponding currents for each of the input voltages added in parallel. The multiplying of each input voltage with each corresponding resistance is executed simultaneously with adding each corresponding current for each input voltage.