Resistive Memory Control Circuit Parasitic Capacitance Management
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Solution Overview
Problem
In semiconductor storage apparatuses, the unipolar type resistance change memory cells face challenges with large parasitic capacitance between peripheral circuits and memory cell arrays, leading to erroneous write or erase operations due to increased distance and wire capacitance, which complicates achieving high-density memory chip integration.
Innovation Solution
The semiconductor storage apparatus includes a memory cell array with rectifying and variable resistive elements connected in series, arranged at crossing points of wires, and a control circuit that sequentially charges wires to specific potentials to manage the potential of selected memory cells, preventing erroneous operations by controlling the selection transistor and data programming.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cell arrays are laminated vertically to increase integration degree, then memory capacity is improved, but parasitic capacitance of wires increases causing erroneous operations
Solution Approach 1:
The patent applies preliminary action by pre-charging adjacent bit lines to a specific potential before the actual write operation. This preparatory charging of neighboring bit lines creates a controlled electrical environment that compensates for parasitic capacitance effects, preventing erroneous operations in vertically laminated memory structures.
Solution Approach 2:
The patent changes electrical parameters by dynamically adjusting the potential of adjacent bit lines during the write operation. By controlling the voltage levels and timing of charge application to neighboring bit lines, the system compensates for parasitic capacitance variations caused by vertical stacking, thereby maintaining operation reliability while achieving high memory capacity.
2Quantity of substance
If distance between peripheral circuits and memory cell arrays is increased to accommodate more layers, then memory density is improved, but wire parasitic capacitance increases
Solution Approach 1:
The patent introduces an intermediary control mechanism that manages the electrical interaction between peripheral circuits and vertically stacked memory cell arrays. By controlling the charging state of adjacent bit lines as an intermediary step, the system mediates the effect of increased wire length and parasitic capacitance, allowing high memory density to be achieved without compromising signal integrity.
3Quantity of substance
If unipolar type operation mode is used to form high-density cell arrays, then integration degree is improved, but susceptibility to parasitic capacitance effects increases
Solution Approach 1:
The patent applies preliminary anti-action by pre-charging adjacent bit lines to counteract the harmful effects of parasitic capacitance before the write operation occurs. This anticipatory measure creates an opposing electrical condition that neutralizes the detrimental impact of parasitic capacitance on unipolar type memory cell operations, ensuring reliable data writing in high-density configurations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively reduces the risk of erroneous resets and set operations by managing parasitic capacitance and voltage application, enhancing the reliability and efficiency of data programming in high-density memory cell arrays.
Implementation Method 1
charging to the first wire connected to a selected memory cell up to a first potential, and then setting the first wire in floating state, and then charging another first wire adjacent to the first wire connected to the selected memory cell up to a second potential, thereby the potential of the first wire connected to the selected memory cell rising up to a third potential by coupling
Implementation Method 2
controlling the selection signal to be supplied to the selection transistor that is connected to the first wire connected to the selected memory cell to charge the first wire to a first potential and then set the first wire in a floating state
Data Source
AI summary
The semiconductor storage apparatus includes a memory cell array including memory cells each having a rectifying element and a variable resistive element connected in series, the memory cells being arranged in crossing portions of a plurality of first wires and a plurality of second wires, and a control circuit configured to control charging to the first wire. The control circuit charges the first wire connected to a selected memory cell up to a first potential, and then set the first wire in a floating state. Then it charges another first wire adjacent to the first wire connected to the selected memory cell to a second potential. The potential of the first wire connected to the selected memory cell is thereby caused to rise to a third potential by coupling.