Resistive Memory Read Circuit with Select Transistor Segmentation
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Solution Overview
Problem
Resistive random-access memory (RRAM) devices face challenges in high power consumption and read disturb due to the need for pre-charging all memory cells during read operations in crossbar arrays, which also shortens endurance from excessive bias voltage and current leakage.
Innovation Solution
A non-volatile memory device architecture that allows concurrent reading of resistive memory cells within a subgroup of the memory array without pre-charging non-selected cells, using select transistors and sense amplifiers to apply read voltage directly to selected cells, reducing the need for global pre-charging and simplifying circuit design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If pre-charging all memory cells is performed during read operations in crossbar arrays, then sneak paths and current leakage are limited, but power consumption increases and read disturb occurs
Solution Approach 1:
The memory array is divided into multiple independently selectable sub-arrays, each with its own select transistor. Only the selected sub-array is activated for read operations, while others remain inactive. This segmentation allows reading from a portion of the memory without pre-charging the entire array, thereby reducing power consumption and avoiding read disturb to non-selected cells while still limiting sneak paths within the active sub-array.
2Reliability
If pre-charging all memory cells is performed during read operations, then current leakage is limited, but read out delays occur
Solution Approach 1:
By segmenting the memory array into selectable sub-arrays and activating only the selected sub-array for read operations, the pre-charge operation is confined to a smaller portion of the memory. This reduces the overall pre-charge time required compared to charging the entire array, thereby reducing read out delays while still effectively limiting current leakage within the active region.
3Productivity
If excessive bias voltage is applied during repeated write and erase cycles, then write and erase operations are performed, but endurance is shortened due to Joule heating and metal ion movements
Solution Approach 1:
The patent applies local quality by assigning individual select transistors to each memory unit, enabling independent control of voltage application to specific regions. This allows write and erase operations to be performed with precise voltage control only where needed, avoiding excessive bias voltage across the entire array. The localized voltage control reduces Joule heating and metal ion movements in non-operational regions, thereby preserving endurance while maintaining write and erase productivity.
4Productivity
If select transistor and resistive memory cells share common node, then concurrent read operation is enabled, but circuit complexity increases
Solution Approach 1:
The patent merges the select transistor with the memory unit structure, where the select transistor's drain is directly connected to the common node shared by multiple resistive memory cells. This integration allows concurrent reading of multiple cells within a memory unit through a single select transistor, enabling parallel operations. While this does increase circuit complexity compared to simpler architectures, it achieves significant productivity gains through concurrent read capability and is justified by the performance benefits.
Data Source
AI summary
A non-volatile memory device includes an array of memory units, each having resistive memory cells and a local word line. Each memory cell has a first and a second end, the second ends are coupled to the local word line of the corresponding memory unit. Bit lines are provided, each coupled to the first end of each resistive memory cell. A plurality of select transistors is provided, each associated with one memory unit and having a drain terminal coupled to the local word line of the associated memory unit. First and second global word lines are provided, each coupled to a control terminal of at least one select transistor. First and second source lines are provided, each coupled to a source terminal of at least one select transistor. The memory device is configured to concurrently read out all resistive memory cells in one selected memory unit in a read operation.