Resistive Memory Read Current Direction for Stability
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Solution Overview
Problem
Resistive memory devices face a high read disturb rate (RDR) due to the increased access frequency of reference cells, leading to stability degradation and reduced sensing margin, as they receive higher read stress compared to normal memory cells.
Innovation Solution
A nonvolatile memory device design featuring a first series connection of a first variable resistor element and a cell transistor, and a second series connection of a second variable resistor element and a reference cell transistor, with first and second current sources providing read currents in opposite directions relative to a shared word line, to minimize RDR and enhance sensing margin.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the reference cell is connected to a plurality of memory cells to enable data reading, then the data reading function is improved, but the reference cell receives high read stress leading to increased read disturb rate and stability degradation
Solution Approach 1:
The patent divides the reference cell into multiple sub-reference cells, each connected to a specific group of memory cells. This segmentation reduces the read stress on each individual sub-reference cell by distributing the access load across multiple units, thereby maintaining reliability while preserving the data reading function.
Solution Approach 2:
The patent changes the operational parameters of the reference cell by applying opposite polarity voltages during read operations. By alternating the voltage polarity and using complementary metal oxide semiconductor (CMOS) circuitry, the reference cell experiences reduced cumulative stress, improving stability while maintaining its reference function for data reading.
2Measurement precision
If the reference cell is frequently accessed to provide reference levels for sensing, then the sensing function is improved, but the read disturb rate increases due to high read stress
Solution Approach 1:
The patent implements periodic action by alternating the polarity of voltages applied to the reference cell in a systematic manner. This periodic voltage reversal prevents cumulative stress buildup in the reference cell, reducing the read disturb rate while maintaining the ability to provide accurate reference levels for sensing operations.
Solution Approach 2:
The patent creates multiple copies of the reference cell structure (sub-reference cells) that can be selectively activated. These copies serve as redundant reference sources, allowing the system to maintain sensing accuracy while distributing the read stress across multiple instances, thereby reducing the read disturb rate on any single reference cell.
3Device complexity
If the reference cell structure is simplified to reduce complexity, then the device complexity is reduced, but the ability to handle high read stress and maintain stability is worsened
Solution Approach 1:
The patent merges the reference cell functionality with complementary metal oxide semiconductor (CMOS) circuitry to create an integrated structure. This combination achieves a balance between simplicity and reliability by using standard CMOS processes to build the reference cell, reducing manufacturing complexity while the opposite polarity voltage technique maintains stability under read stress.
Data Source
AI summary
A nonvolatile memory device includes a memory cell comprising a first variable resistor having one end connected to a first node, and the other end connected to a second node through a cell transistor; and a reference cell comprising a second variable resistor having one end connected to a third node, and the other end connected to a fourth node through a reference cell transistor, wherein gates of the cell transistor and the reference cell transistor are connected to a word line. Directions of a first read current flowing in the memory cell and a direction of a second read current flowing in the reference cell are opposite to each other.