Resistive Memory Read Unit Stabilization Timer
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Solution Overview
Problem
In semiconductor devices with resistive material based memory arrays, such as PRAM, RRAM, and MRAM, reading data before it stabilizes can result in incorrect readings due to the need for time to settle in set or reset states after data writing.
Innovation Solution
Implementing a read unit that disables read operations for a specified time period following data writing, either based on a pre-set timer, matching write addresses, or a combination of these, to ensure data stability before reading.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If read operation is enabled immediately after write operation, then productivity is improved, but measurement precision deteriorates due to incorrect readings from unstable data
Solution Approach 1:
The patent implements a recovery timer that pre-determines a stabilization period after write operations before allowing read operations. This preliminary action ensures data stability is achieved before reading, preventing incorrect readings while maintaining efficient operation timing.
Solution Approach 2:
The read unit monitors the output stability of memory cells and uses this feedback to control whether read operations are enabled. When data becomes stable after writing, the feedback signal allows the read unit to proceed; otherwise, it blocks the read operation to prevent incorrect readings.
2Measurement precision
If read operation is disabled for stabilization period, then measurement precision is improved, but productivity deteriorates due to reduced read speed
Solution Approach 1:
The recovery timer pre-calculates and enforces a fixed stabilization period after write operations. This preliminary timing action ensures that reads only occur after data is guaranteed to be stable, maintaining high read accuracy without unnecessarily delaying reads beyond the required stabilization time.
Solution Approach 2:
The system dynamically adjusts read operation timing based on whether a write operation recently occurred. The read unit is conditionally enabled or disabled based on the recovery timer status, creating a dynamic control mechanism that optimizes both accuracy and speed by allowing reads as soon as stability is achieved.
3Productivity
If multiple data words are written simultaneously, then productivity is improved, but device complexity increases due to need for address matching logic
Solution Approach 1:
The patent segments the write address space into multiple independent write buffers, each with its own recovery timer and address matching logic. This segmentation allows simultaneous writes to different memory regions while keeping each control unit relatively simple, managing complexity through modular division.
Solution Approach 2:
The address buffer and recovery timer mechanism serves multiple functions: it tracks write operations, determines stabilization timing, and controls read enablement for multiple data words. This multi-functionality reduces the need for separate control circuits for each write operation, managing complexity while supporting parallel writes.
Data Source
AI summary
One embodiment includes a non-volatile memory cell array, and a read unit configured to disable read operation for the non-volatile memory cell array for a time period following writing of data in the non-volatile memory cell array.