Two-Terminal Resistive Memory Architecture With Recessed Conductive Layers
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Solution Overview
Problem
Current resistive memory technologies face challenges in achieving high-density, low-fabrication-cost memory solutions with effective leakage current mitigation and scalable technology nodes, particularly in three-dimensional architectures.
Innovation Solution
The development of a two-terminal memory architecture with oblique angle layer arrangements and a method involving a via etch process to form recesses in conductive layers, incorporating selection and switching materials to reduce leakage current and enhance memory density, integrated with CMOS devices on an insulated semiconductor substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional resistive memory architectures are used, then fabrication processes are simpler, but memory density is lower and leakage current is higher
Solution Approach 1:
The patent transitions from planar two-terminal memory structures to three-dimensional architectures by stacking multiple memory layers vertically. Each layer includes alternating conductive layers and insulating layers with memory elements formed at intersections, enabling high-density storage while maintaining compatibility with standard CMOS fabrication processes
Solution Approach 2:
The patent implements nested structures where conductive layers are embedded within insulating layers, and memory elements are formed within the three-dimensional lattice of alternating layers. This nested arrangement maximizes space utilization and achieves high memory density without proportionally increasing fabrication complexity
2Object-generated harmful factors
If conventional memory architectures are used, then fabrication cost is lower, but leakage current mitigation is insufficient
Solution Approach 1:
The patent introduces selector devices as intermediary components between bitlines and memory elements. These selectors act as gatekeepers that control current flow, enabling precise selection of target memory cells and preventing leakage current from affecting non-selected cells, thereby improving signal integrity without requiring complex additional fabrication steps
Solution Approach 2:
The patent applies different material compositions and structural configurations to specific regions of the memory device. Selector devices in critical paths use optimized materials and geometries to minimize leakage, while other regions maintain standard configurations, achieving localized leakage mitigation without uniformly increasing fabrication complexity
3Quantity of substance
If scaling to smaller technology nodes is pursued, then memory density increases, but maintaining thermal budgets becomes difficult
Solution Approach 1:
The patent divides the memory structure into multiple thin alternating layers of conductive and insulating materials. This segmentation reduces the thickness of individual layers, allowing heat to dissipate more efficiently through the layered structure and preventing excessive temperature buildup during fabrication and operation, thereby enabling scaling to smaller technology nodes while maintaining thermal budgets
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in high-density, low-cost memory solutions with reduced leakage current, enabling efficient memory operations and scalability down to small technology nodes, such as 5 nanometers, while maintaining thermal budgets and using few masks.
Implementation Method 1
The conductive structure could be formed from ions, atoms that can be ionized under appropriate circumstances (e.g., a suitable electric field)
Implementation Method 2
resistive switching is a result of formation of a conductive structure within an otherwise electrically insulating medium
Implementation Method 3
field-assisted diffusion of atoms can occur in response to a suitable electric potential applied to a resistive memory cell
Implementation Method 4
formation of the conductive filament can occur in response to joule heating and electrochemical processes in binary oxides
Implementation Method 5
by a redox process for ionic conductors including oxides, chalcogenides, polymers, and so on
Data Source
AI summary
Providing a high-density two-terminal memory architecture(s) having performance benefits of two-terminal memory and relatively low fabrication cost, is described herein. By way of example, the two-terminal memory architecture(s) can be constructed on a substrate, in various embodiments, and comprise two-terminal memory cells formed within conductive layer recess structures of the memory architecture. In one embodiment, a conductive layer recess can be created as a horizontal etch in conjunction with a vertical via etch. In another embodiment, the conductive layer recess can be patterned for respective conductive layers of the two-terminal memory architecture.