Resistive Memory Reference Cell Read Circuit
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Solution Overview
Problem
Resistive memory devices face challenges in accurately reading data due to resistance and parasitic capacitance on the path of the read current, which limits reading speed.
Innovation Solution
The resistive memory device includes a cell array with memory cells and reference cells, column switch circuits, and a control circuit that generates a read control signal to provide precharge and read currents, allowing for accurate and high-speed data reading by comparing voltages across the memory and reference cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If read current is supplied to the memory cell to detect stored data, then data reading function is achieved, but resistance on the read current path hinders accurate reading
Solution Approach 1:
A sense amplifier is introduced as an intermediary component between the memory cell and the readout circuitry. The sense amplifier detects the voltage level at the bit line by comparing it against a reference voltage, effectively mediating the measurement process and isolating the read operation from the resistance interference in the memory cell path.
Solution Approach 2:
The patent employs dynamic adjustment of read current magnitude and duration based on the detected voltage level. By changing the parameters of the read current (strength, pulse width) according to the initial voltage detection, the system optimizes the reading process to overcome resistance effects while maintaining accurate data retrieval.
2Productivity
If read current flows through the memory cell path, then data can be read, but parasitic capacitance on the path limits reading speed
Solution Approach 1:
The sense amplifier is pre-charged to a reference voltage level before the actual read operation begins. This preliminary action prepares the detection circuitry in advance, so that when the read current is applied, the voltage comparison can occur immediately without waiting for capacitance charging, thereby overcoming the speed limitation imposed by parasitic capacitance.
Solution Approach 2:
The reading process is structured as a periodic sequence: pre-charge the sense amplifier, apply read current pulse, detect voltage level, then reset and repeat. By using periodic pulsing of the read current and synchronized detection cycles, the system manages the parasitic capacitance effects through rhythmic operation rather than continuous operation, improving overall reading speed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables accurate and rapid data reading by reducing resistance differences and quickly charging capacitance, thereby improving reading speed and reliability.
Implementation Method 1
providing precharge currents to the memory cell and the reference cell, respectively, and providing a pumping current to the reference resistor circuit
Implementation Method 2
quickly charging capacitance
Implementation Method 3
comparing voltages according to the read currents to produce a comparison signal
Data Source
AI summary
A resistive memory device according to an example embodiment of the inventive concepts includes: a cell array including a first section and a second section; a first column switch circuit connected to a memory cell and a reference cell of the first section through first bit lines; a second column switch circuit connected to a memory cell and a reference cell of the second section through second bit lines; and a column decoder configured to control the first and second column switch circuits such that one of the first bit lines connected to the memory cell and one of the second bit lines connected to the reference cell are selected according to a first column address, and one of the first bit lines connected to the reference cell and one of the second bit lines connected to the memory cell are selected according to a second column address.