Resistive Memory Reference Cell Array Position Compensation
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Solution Overview
Problem
Next-generation memory devices require adaptive reference current generation based on memory cell position and chip temperature for accurate data reading, while existing technologies face challenges with temperature compensation and sneak current issues, especially as memory cell arrays increase in size.
Innovation Solution
A resistive memory device with a normal cell array, a reference cell array, and a sense amplifier circuit that generates a reference current based on the resistance states of memory cells, including a reference cell selector to adaptively select sub-arrays and neighboring cells for temperature and position compensation, and a method to repair defective reference cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a reference cell array is used to generate reference current for sensing memory cell data, then data reading accuracy is improved, but read errors occur due to temperature variations and position-dependent resistance changes
Solution Approach 1:
The patent applies parameter changes by selectively programming resistance states of reference cells based on their position in the array. Different reference cells are programmed to have different resistance values that compensate for position-dependent resistance variations and temperature effects, enabling accurate reference current generation across the entire memory array
Solution Approach 2:
The patent implements local quality by programming each reference cell with a specific resistance state tailored to its local position in the array. Reference cells at different locations (e.g., near vs. far from sensing circuitry) are programmed differently to account for local temperature gradients and resistance variations, ensuring accurate compensation at each position
2Quantity of substance
If the memory cell array size is increased to meet high capacity demands, then storage capacity is improved, but sneak current issues and temperature compensation difficulties worsen
Solution Approach 1:
The patent applies segmentation by dividing the reference cell array into multiple sub-arrays, each handling a specific region of the memory cell array. This segmentation allows independent programming and control of reference cells for different regions, enabling better management of sneak currents and temperature compensation in large-scale memory structures
Solution Approach 2:
The patent uses parameter changes by programming reference cells with specific resistance states to suppress sneak currents. By adjusting the resistance values of reference cells based on their position and the local memory cell configuration, the patent enables accurate sensing while minimizing harmful sneak current effects in large-capacity memory arrays
3Reliability
If adaptive reference current generation based on position and temperature is implemented, then sensing margin is improved, but device complexity increases
Solution Approach 1:
The patent implements self-service by programming reference cells to automatically compensate for temperature and position effects without requiring external control circuits. The reference cells themselves are configured with appropriate resistance states to generate the correct reference current for their local conditions, eliminating the need for complex adaptive control logic
Solution Approach 2:
The patent applies preliminary action by pre-programming the resistance states of reference cells during manufacturing or initialization. The reference cells are configured in advance to account for position-dependent and temperature-dependent variations, so that during normal operation, the correct reference current is generated automatically without real-time adjustment circuits
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution ensures accurate data reading by minimizing read errors through adaptive reference current generation, securing sensing margins, and improving yield by performing position and temperature compensation, as well as repairing defective reference cells.
Implementation Method 1
generating a cell current according to a resistance state of a memory cell selected among the plurality of memory cells based on an input address
Data Source
AI summary
A resistive memory device includes: a normal cell array suitable for including a plurality of memory cells and generating a cell current according to a resistance state of a memory cell selected based on an input address; a reference cell array suitable for including a plurality of sub-arrays each including a predetermined number of memory cells, and generating a reference current according to a combination of resistance states of memory cells of a sub-array, the sub-array being selected based on a reference selection signal; a sense amplifier circuit suitable for sensing and amplifying a signal indicative of data of the selected memory cell based on the cell current and the reference current during a read operation; and a reference cell selector suitable for generating the reference selection signal, the sub-array in the reference cell array corresponding to a position of the selected memory cell in the normal cell array.