Resistive Memory Refresh via Resistance State Grouping
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Solution Overview
Problem
Next-generation memory devices require a balance between high integrity, non-volatility, and high speed, which existing technologies struggle to achieve, particularly in resistive memory devices where data retention and refresh operations are inefficient due to varying resistance states.
Innovation Solution
A method for operating resistive memory devices that involves determining the need for a refresh operation based on resistance states, applying current pulses or bias voltages to adjust resistance levels, and performing re-writing operations on memory cells with low resistance states to maintain data integrity and reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If refresh operations are performed on all memory cells, then data retention reliability is improved, but power consumption increases
Solution Approach 1:
The patent applies local quality by differentiating refresh operations based on resistance state groups. Memory cells are divided into first group (higher resistance) and second group (lower resistance), with different refresh frequencies applied to each group. This selective approach ensures that cells needing refresh receive it while reducing unnecessary refresh operations on cells with good retention, thereby improving reliability where needed and reducing power consumption overall.
Solution Approach 2:
The patent implements dynamics by making refresh operations adaptive rather than static. The refresh frequency is dynamically adjusted based on the resistance state of each memory cell group. By monitoring resistance states and adjusting refresh rates accordingly, the system optimizes the balance between maintaining data integrity and minimizing power consumption, allowing the refresh strategy to evolve based on actual cell conditions.
2Reliability
If refresh operations are performed frequently, then data integrity is improved, but writing speed decreases
Solution Approach 1:
The patent applies local quality by implementing different refresh frequencies for different memory cell groups based on their resistance states. The first group (higher resistance) and second group (lower resistance) receive tailored refresh schedules, ensuring data integrity for cells that need it while minimizing refresh interruptions for cells with good retention, thus maintaining writing speed where possible.
Solution Approach 2:
The patent implements periodic action through scheduled refresh operations at different intervals for different cell groups. By establishing periodic refresh cycles based on resistance state characteristics, the system maintains data integrity through regular refreshes where needed while allowing longer intervals for stable cells, reducing the overall impact on writing speed and productivity.
3Reliability
If memory cells with lower resistance states are refreshed, then data retention is improved, but device complexity increases
Solution Approach 1:
The patent applies local quality by identifying and selectively refreshing memory cells based on their resistance state groups. By categorizing cells into first group (higher resistance) and second group (lower resistance) and applying different refresh strategies, the system improves data retention for vulnerable cells without unnecessarily complicating the device architecture, as the differentiation is based on inherent cell properties rather than additional complex structures.
Solution Approach 2:
The patent implements self-service by utilizing the inherent resistance state characteristics of memory cells to determine refresh needs. The system leverages the natural variation in resistance states as a self-indicating mechanism for refresh requirements, eliminating the need for external monitoring or complex control logic to identify which cells need refreshing, thus improving retention while minimizing added complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves data reliability and reduces power consumption by selectively refreshing memory cells with poor data retention characteristics, maintaining the balance of integrity, non-volatility, and speed in resistive memory devices.
Implementation Method 1
a bias voltage may be applied to the first memory cell so that a filament is generated in a variable resistance device in the first memory, and a bias voltage may be applied to the second memory cell so that a filament in a variable resistance device is cut
Implementation Method 2
The performing of the re-writing operation may include applying a current pulse to the first memory cell
Data Source
AI summary
A method of operating a resistive memory device including a plurality of memory cells comprises determining whether to perform a refresh operation on memory cells in a memory cell array; determining a resistance state of each of at least some of the memory cells; and performing a re-writing operation on a first memory cell having a resistance state from among a plurality of resistance states that is equal to or less than a critical resistance level.