Resistive Memory Reset Voltage Control Circuit
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In resistive memory devices, the reset operation can lead to erroneous set operations due to voltage drops across parasitic resistances in the wiring, causing unintended changes in memory cell states, especially when multiple memory cells are reset simultaneously.
Innovation Solution
A control circuit is implemented to apply a control voltage necessary for transitioning a variable resistance element from a low to a high resistance state, with the voltage value in initial applications set to the minimum required for all memory cells, and subsequently increased by a certain value in subsequent operations, ensuring that the voltage applied does not exceed the necessary threshold for set operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a voltage larger than necessary for reset operation is applied to compensate for wiring resistance, then the desired reset current can be supplied to the selected memory cell, but a voltage exceeding the set threshold may be applied causing erroneous set operations
Solution Approach 1:
The patent applies a dynamically adjusted reset voltage that is tailored to each memory cell's specific characteristics. The control circuit determines an optimal reset voltage for each cell that compensates for wiring resistance without exceeding the set threshold, transforming the static voltage application into a dynamic, cell-specific process that prevents erroneous set operations while ensuring reliable reset operations
Solution Approach 2:
The patent changes the voltage parameter from a fixed value to a cell-specific optimized value. By determining individual reset voltages for each memory cell based on their unique resistance characteristics and wiring path, the system adjusts the voltage parameter to achieve reliable reset operations without causing erroneous set operations in other cells
2Productivity
If multiple memory cells are reset simultaneously, then productivity is improved, but voltage drops across parasitic resistances cause unintended changes in memory cell states
Solution Approach 1:
The patent segments the reset operation into individual cell-specific voltage applications. Instead of applying a single voltage to multiple cells simultaneously, the control circuit determines and applies customized reset voltages to each memory cell individually, preventing voltage drops from affecting other cells while maintaining overall operation efficiency
Solution Approach 2:
The patent applies local quality by tailoring the reset voltage to each specific memory cell's characteristics and its unique wiring path. Each cell receives a customized voltage that accounts for its local parasitic resistance, ensuring that reset operations on one cell do not inadvertently affect the state of other cells
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach prevents erroneous set operations by maintaining the voltage below the set threshold, even with parasitic resistances, and ensures stable reset operations by adjusting the voltage increment based on the distribution of voltage values across memory cells.
Implementation Method 1
the variable resistance element changes from a high resistance state to a low resistance state
Data Source
AI summary
A semiconductor storage device includes: a memory cell array including memory cells, each of the memory cells having a variable resistance element; and a control circuit configured to apply a control voltage, which is necessary for the variable resistance element to transit a resistance state, to a selected memory cell. When applying the control voltage plural times, the control circuit operates to set a value of the control voltage applied in a first control voltage application operation to be substantially equal to a minimum value of distribution of the voltage values of all the memory cells in the memory cell array required to transit the resistance state of the variable resistance element from a high resistance state to a low resistance state. The control circuit operates to perform a plurality of control voltage application operations by increasing the value of the control voltage by a certain value.