Resistive Memory Cell with Bidirectional Row and Column Access
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Solution Overview
Problem
Current resistive memory devices face challenges in efficiently performing bidirectional read and write operations, which are essential for neuromorphic systems that mimic biological neural networks, due to limitations in the design of memory cell arrays and access mechanisms.
Innovation Solution
A resistive memory device with a memory cell array arranged in a matrix, featuring variable resistors connected to bit lines, row transistors, and column transistors, allowing for bidirectional access through row and column word lines, with sense amplifiers and write drivers to manage data storage and retrieval.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a conventional memory cell array design is used, then the structure is simple, but bidirectional read and write operations cannot be performed efficiently
Solution Approach 1:
The memory cell array is segmented into multiple memory cells arranged in a matrix, with each memory cell independently controllable through row and column transistors. This segmentation enables bidirectional access by allowing selective activation of specific rows and columns, resolving the contradiction between versatility and complexity.
Solution Approach 2:
The patent introduces a two-dimensional matrix arrangement of memory cells with row and column dimensions, enabling access from multiple directions (row direction and column direction). This dimensional approach allows bidirectional read and write operations, transforming a single-access-direction structure into a multi-directional access structure.
2Productivity
If bidirectional read and write operations are implemented, then neuromorphic system performance is improved, but power consumption increases
Solution Approach 1:
The patent implements dynamic control of row and column transistors through word lines, allowing the memory device to adaptively select access directions based on operation requirements. This dynamic switching capability enables efficient bidirectional operations while minimizing unnecessary transistor activations, thereby reducing power consumption compared to static designs.
Solution Approach 2:
The patent applies local quality control by enabling only the specific row or column transistors needed for each operation. Instead of activating entire arrays, the design allows selective activation of individual memory cells or small groups, reducing the overall power consumption while maintaining high operation efficiency for neuromorphic applications.
3Loss of time
If bidirectional access is enabled, then access time is reduced, but device complexity increases
Solution Approach 1:
The patent merges row and column transistor controls into a unified memory cell structure, where both transistors work together to enable bidirectional access. This merging approach allows simultaneous row and column selection, reducing access time by enabling direct access from either direction without requiring additional switching steps, while sharing common circuit elements to manage complexity.
Data Source
AI summary
A resistive memory device includes a memory cell array in which a plurality of memory cells are arranged. Each of the plurality of memory cells includes a variable resistor comprising a first end connected to a bit line, and a second end, a row transistor connected between a row source line and the second end of the variable resistor, the row transistor being selectable by a row word line, and a column transistor connected between a column source line and the second end of the variable resistor, the column transistor being selectable by a column word line. Based on the row transistor being selected, first data is written or second data is read in a row direction of the memory cell array, and based on the column transistor being selected, the first data is written or the second data is read in a column direction of the memory cell array.