Resistive Memory Scheduler for Autonomous Maintenance
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Solution Overview
Problem
Emerging memory technologies face challenges in maintaining reliable storage levels over time due to degradation mechanisms, which can lead to increased overhead, delays, and chip size associated with error correction codes and frequent refresh operations, especially when compared to traditional DRAM and Flash architectures.
Innovation Solution
An integrated circuit with a memory scheduler that intelligently schedules internal maintenance operations, such as built-in self-test and self-repair, in response to sensor signals and external commands, ensuring transparent operation to external devices, thereby maintaining storage levels without affecting external system performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction code (ECC) algorithms and additional bits are used to improve reliability, then detection and repair of failing memory cells is enabled, but chip size increases and operation delays occur due to ECC calculations
Solution Approach 1:
The memory device performs built-in self-repair (BISR) operations autonomously using sensor signals to detect degradation and trigger maintenance operations. The system monitors its own health status through temperature sensors, operation cycle counters, and voltage sensors, automatically initiating repair sequences without external intervention or complex ECC hardware
Solution Approach 2:
The system performs maintenance operations proactively based on predicted degradation patterns. By monitoring operation cycles, temperature exposure, and voltage conditions, the system triggers repair operations before failures occur, preventing the need for complex error correction mechanisms
2Reliability
If error correction code (ECC) algorithms are implemented to improve reliability, then detection and repair of failing memory cells is enabled, but operation delays occur due to ECC calculations
Solution Approach 1:
The system performs maintenance operations periodically based on monitored parameters such as operation cycle counts and temperature thresholds. This periodic self-refresh approach maintains reliability without requiring continuous ECC calculations, significantly reducing operational delays
Solution Approach 2:
The memory device autonomously performs self-diagnosis and self-repair operations using integrated sensors and control logic, eliminating the need for external ECC processing and associated time delays
3Reliability
If frequent refresh operations are performed to maintain storage levels, then reliability is improved, but overhead and chip size increase
Solution Approach 1:
The refresh operation frequency is dynamically adjusted based on real-time sensor feedback regarding actual degradation rates. The system increases refresh frequency only when degradation is detected and reduces it when storage levels are stable, optimizing overhead while maintaining reliability
Solution Approach 2:
The system changes operational parameters such as refresh intervals and maintenance operation timing based on monitored conditions including temperature, operation cycles, and voltage levels, allowing adaptive optimization of overhead
Data Source
AI summary
An integrated circuit includes: a resistive memory having an array of resistive memory cells; a memory controller that controls operation of the resistive memory in accordance with external commands from an external device; and a memory scheduler coupled to the resistive memory and to the memory controller. The memory scheduler schedules internal maintenance operations within the resistive memory in response to trigger conditions indicated by at least one sensor signal or external command. The operation of the memory scheduler and performance of the internal maintenance operations are transparent to the external device and, optionally, transparent to the memory controller.