Resistive Memory Second Write Driver Surge Current

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Solution Overview

Problem

Next-generation memory devices require high integrity, non-volatility, and high speed, but existing resistive memory devices face challenges in preventing surge currents due to parasitic capacitance, which affects durability and data reliability.

Innovation Solution

The resistive memory device incorporates a second write driver that converts write voltage into write current, reducing the influence of parasitic capacitance by providing the current directly to the memory cell, and adjusts write voltage and current based on the number of program loops to improve resistance variation control.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If write voltage is applied directly to the memory cell array, then write speed is improved, but surge current flows through the memory cell due to parasitic capacitance

Engineering Contradiction:
Improvewrite speedVSAvoiddata reliability
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

A second write driver is introduced as an intermediary component between the first write driver and the memory cell array. The second write driver converts the write voltage from the first write driver into write current, which is then supplied to the selected memory cell. This intermediary conversion process eliminates the direct application of voltage that causes surge current, while still achieving fast write speeds through controlled current delivery.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent replaces the direct voltage-driven mechanism with a current-driven mechanism. Instead of applying write voltage directly to the memory cell array (voltage-driven approach), the system uses the second write driver to convert this into write current (current-driven approach). This substitution of the driving mechanism eliminates the harmful voltage surge effect caused by parasitic capacitance while maintaining write performance.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Productivity

If write voltage is increased to improve programming speed, then program loop efficiency is improved, but resistance variation control deteriorates

Engineering Contradiction:
Improveprogram loop efficiencyVSAvoidresistance variation control
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The patent changes the critical parameter from voltage to current for the write operation. By using the second write driver to convert write voltage into write current, the system can control the magnitude of current precisely regardless of the voltage level. This parameter change allows for high programming speed (through sufficient current magnitude) while maintaining precise resistance variation control (through controlled current delivery to only the selected memory cell).

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This solution enhances the durability and data reliability of the memory device by preventing surge currents and allowing precise adjustment of resistance states, thereby meeting the demands for high integrity and speed.

Implementation Method 1

a second write driver disposed between the memory cell array and the first write driver and configured to provide a write current generated based on the write voltage to a first signal line selected from among the plurality of first signal lines

Methodology Applied
Scientific EffectVoltage to current conversion: Ohm's Law

Data Source

PatentUS9613697B2Resistive memory device
Publication Date: 2017.04.04 SAMSUNG ELECTRONICS CO LTD
  • US9613697B2 patent drawing
  • US9613697B2 patent drawing
  • US9613697B2 patent drawing

AI summary

A resistive memory device includes a memory cell array having a plurality of memory cells respectively connected to a plurality of first signal lines and a plurality of second signal lines crossing each other. A first write driver is configured to provide a write voltage to write data to the memory cells. A second write driver is configured to be disposed between the memory cell array and the first write driver and provide a write current generated based on the write voltage to a first signal line selected from among the plurality of first signal lines.