Resistive Memory Leakage Current Control via Selection Lines
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Solution Overview
Problem
Resistive memory devices face challenges with leakage current and power consumption due to current flow through unintended memory cells during data read operations, which affects the efficiency and reliability of data storage.
Innovation Solution
The resistive memory device incorporates upper and lower selection lines that are activated or deactivated in response to read commands, minimizing leakage current and optimizing power consumption by ensuring current flows only through selected memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If current is applied to read data from memory cells, then data can be read from the memory device, but leakage current occurs through unintended memory cells causing increased power consumption
Solution Approach 1:
The memory array is segmented into multiple blocks with isolated read paths. Each block has its own set of word lines and bit lines that are independently controllable, allowing selective activation of only the block containing the target memory cell for reading, thereby preventing current flow through other blocks
Solution Approach 2:
Isolation transistors are introduced as intermediary elements between adjacent memory blocks. These transistors act as switches that can be controlled to either connect or disconnect bit lines between blocks, ensuring that current flows only through the selected block during read operations and preventing leakage into neighboring blocks
2Ease of operation
If current flows through all memory cells connected to selected row and column lines, then data can be accessed, but unintended memory cells experience current flow causing leakage
Solution Approach 1:
The isolation transistors are strategically positioned at specific locations where bit lines intersect between adjacent blocks. These transistors provide localized control over current flow paths, ensuring that only the specific memory cell at the intersection of activated word line and bit line experiences current flow, while neighboring cells remain isolated
Solution Approach 2:
The isolation transistors are dynamically controlled based on the read operation requirements. Their gate voltages are adjusted in real-time to enable or disable current flow through specific bit line segments, allowing the system to adaptively route current only through the intended memory cell during each read operation
Data Source
AI summary
A resistive memory device includes: a substrate; a plurality of row lines extending in a first direction and spaced apart from each other in a second direction and a third direction, on the substrate, wherein the first direction, the second direction, and the third direction intersect each other; a plurality of column lines extending in the second direction and spaced apart from each other in the first direction, on the substrate; a plurality of upper selection lines extending in the second direction, between the row lines and the column lines; a channel layer extending in the third direction and connected to the plurality of row lines; and a first impurity region and a second impurity region spaced apart from each other in the third direction with the upper selection line interposed therebetween.