Resistive Memory Device Self-Aligning Manufacturing Method
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Solution Overview
Problem
The design rules for via holes or contact holes in the back end of line (BEOL) of resistive memory devices are larger than those in the front end of line (FEOL) or middle end of line (MEOL), affecting the manufacturing of small-sized resistive memory devices and limiting memory cell density.
Innovation Solution
A manufacturing method that uses line-type patterns to form self-align openings and define memory cell positions, involving a stacked structure with impurity diffusion layers, insulating layers, and signal lines, allowing for the formation of memory material layers and second signal lines perpendicular to the first signal lines, eliminating the need for conventional via holes or contact holes in BEOL.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional via holes or contact holes are formed in BEOL with larger design rules, then manufacturing process is simpler, but memory cell density and device scaling are limited
Solution Approach 1:
The manufacturing process is divided into multiple etching stages (first etching to form second implanted stacked structures, second etching to form third implanted stacked structures), allowing progressive formation of complex patterns while maintaining control over each individual step
Solution Approach 2:
Impurity diffusion layers are pre-formed in stacked configurations before the etching process, creating self-aligning structures that automatically define the positions of memory cells and signal lines, eliminating the need for separate alignment operations
2Manufacturing precision
If line-type patterns are used to form self-align openings, then memory cell density is enhanced, but manufacturing process complexity increases
Solution Approach 1:
The stacked impurity diffusion structures serve as self-aligning masks that automatically define the positions of openings and signal lines during etching, eliminating the need for separate alignment operations and reducing manufacturing complexity despite the multi-step process
Solution Approach 2:
The invention transitions from planar via hole formation to three-dimensional stacked impurity diffusion structures, utilizing vertical layering to achieve self-alignment and enable higher density memory cell arrangements
3Manufacturing precision
If stacked impurity diffusion structures are formed, then self-align openings are defined, but process steps increase
Solution Approach 1:
Multiple functions are merged into the stacked impurity diffusion structures: they serve as memory cell definitions, self-aligning masks for etching, and precursors for signal line formation, reducing the need for separate process steps despite the initial complexity of forming the stacks
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly enhances memory cell density and enables the production of resistive memory devices with improved scaling characteristics, suitable for high-density memory applications.
Implementation Method 1
a first implanted stacked structure having a first impurity diffusion layer, a second impurity diffusion layer, and a third impurity diffusion layer is formed in a substrate
Implementation Method 2
the first implanted stacked structure is etched to form a plurality of second implanted stacked structures
Data Source
AI summary
A method of manufacturing resistive memory includes the steps: forming a first implanted stacked structure having a first impurity diffusion layer, a second impurity diffusion layer, and a third impurity diffusion layer in a substrate; etching at least the first implanted stacked structure to form a plurality of second implanted stacked structures, wherein the first impurity diffusion layers are first signal lines; forming a plurality of first insulating layers between the second implanted stacked structures; etching the second implanted stacked structures to form a plurality of third implanted stacked structures, wherein the first signal lines are not etched; forming a plurality of second insulating layers between the third implanted stacked structures; forming a plurality of memory material layers electrically coupled to the third impurity diffusion layers; and forming a plurality of second signal lines perpendicular to the first signal lines and electrically coupled to the memory material layers.