Resistive Memory Sensing via Reference Current Division

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Resistive memory devices face performance degradation due to manufacturing variations and signal variations in peripheral circuits, leading to challenges in achieving high integration and data sensing performance.

Innovation Solution

A resistive memory device design incorporating a first and second resistive memory cell, a reference current generator, and bitline sense amplifiers that generate and divide reference currents to sense data, allowing for simultaneous sensing of data from multiple cells with high integration and performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If a conventional resistive memory device design is used, then the device can be manufactured with standard processes, but the data sensing performance degrades due to manufacturing variations and signal variations in peripheral circuits

Engineering Contradiction:
Improvedata sensing performanceVSAvoidperformance stability
Core Design Contradiction:
Measurement precisionVSReliability

Solution Approach 1:

The patent changes the electrical parameters by providing different reference currents (first reference current and second reference current with different amounts) to different sense amplifiers. This parameter differentiation compensates for manufacturing variations and signal variations, thereby improving data sensing performance and reliability without requiring additional complex circuits

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent applies local quality by tailoring the reference current characteristics to specific sense amplifiers. Each sense amplifier receives a customized reference current based on its position and characteristics in the memory device, which compensates for local variations in manufacturing and signal conditions, thereby improving overall sensing performance

Inventive Principle:
Principle #3Local quality

2Measurement precision

If additional circuits are added to improve sensing performance, then data sensing accuracy improves, but the integration degree and device complexity decrease

Engineering Contradiction:
Improvedata sensing accuracyVSAvoidintegration degree
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The reference current generator performs multiple functions: it generates both the first reference current and the second reference current with different amounts, and these currents are used to compensate for variations in different sense amplifiers. This multi-functionality improves sensing accuracy without requiring separate compensation circuits for each sense amplifier, thereby maintaining high integration

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Device complexity

If uniform reference currents are provided to all sense amplifiers, then the circuit design is simplified, but performance degradation occurs due to manufacturing and signal variations

Engineering Contradiction:
Improvecircuit design simplicityVSAvoidsensing performance
Core Design Contradiction:
Device complexityVSMeasurement precision

Solution Approach 1:

The patent changes the reference current parameters by providing different amounts of reference currents to different sense amplifiers. This parameter differentiation maintains relatively simple circuit design while effectively compensating for manufacturing and signal variations, thereby improving sensing performance without significantly increasing circuit complexity

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS9368178B2Resistive memory device, memory system including the same and method of reading data from the same
Publication Date: 2016.06.14 SAMSUNG ELECTRONICS CO LTD
  • US9368178B2 patent drawing
  • US9368178B2 patent drawing
  • US9368178B2 patent drawing

AI summary

A resistive memory device may include first and second resistive memory cells, a reference current generator, and first and second bitline sense amplifiers. The reference current generator may be configured to apply the first and second reference currents to a first common node. A total reference current of the first reference current and the second reference current provided to the first common node may be divided into a first sensing current and a second sensing current by the first common node. The first and second sensing currents may be provided to the first and second bitline sense amplifiers by the first common node, respectively. The first and second bitline sense amplifiers may be configured to sense first data of the first resistive memory cell and second data of the second resistive memory cell based on the first and second sensing currents, respectively.