Resistive Memory Cell Layout With Shared Reset Transistors
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Solution Overview
Problem
Next-generation memory devices face challenges in achieving high integrity, non-volatility, high speed, and reduced occupied area, which existing technologies have not adequately addressed.
Innovation Solution
A resistive memory device design that includes a memory cell array with resistive memory cells and reset transistors, where adjacent word-lines share a common source line, and transistors operate in saturation regions, enabling efficient set and reset write operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If each word-line has its own dedicated reset transistor, then reset operation reliability is improved, but device occupied area increases
Solution Approach 1:
Adjacent word-lines share a common reset transistor, merging the reset functions for multiple word-lines into a single transistor component. This reduces the total number of reset transistors required in the memory array, thereby decreasing the occupied area while maintaining reliable reset operations through proper selection transistor control
Solution Approach 2:
The shared reset transistor serves multiple word-lines simultaneously, making it a universal component that performs the reset function for more than one word-line. This multi-functionality approach allows a single transistor to replace what would traditionally require multiple dedicated transistors, reducing overall device area
2Ease of operation
If transistors operate in linear region, then current control flexibility is improved, but power consumption increases
Solution Approach 1:
The patent changes the operating region parameter of the transistors from linear region to saturation region. This parameter change allows the transistors to operate with higher current drive capability and lower power consumption, as the saturation region provides more efficient current control for the set and reset write operations
3Speed
If sufficient write current is applied, then write operation speed is improved, but power consumption increases
Solution Approach 1:
By changing the transistor operating region to saturation, the patent achieves higher current drive capability that enables faster write operations. The saturation region provides the necessary current magnitude for rapid resistive memory cell switching while improving power efficiency compared to linear region operation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces occupied area, enhances performance by generating sufficient set current, and lowers power consumption while maintaining uniformity characteristics of resistive memory cells.
Implementation Method 1
a variable resistor element coupled to a first source line among the plurality of source lines
Data Source
AI summary
A resistive memory device includes a memory cell array, a write/read circuit, and a control circuit. The memory cell array includes resistive memory cells and reset transistors, each of the reset transistors is coupled to respective one of source lines, and each of the source lines is between a respective pair of adjacent word-lines. A first resistive memory cell includes a variable resistor element that is coupled to a first source line among the plurality of source lines, and a first selection transistor. The first selection transistor is coupled to a first bit-line, the variable resistor element, and a first word-line. The first bit-line is coupled to the column decoder and a first write driver of the write/read circuit. The first write driver is configured to perform a set write operation using the first selection transistor and to perform a reset write operation using the first reset transistor.