Resistive Memory Shared Source-Line Layout for Uniform Write Voltage
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Solution Overview
Problem
Bipolar-type resistive memory arrays face challenges in achieving high area efficiency while maintaining reliability due to the need for bidirectional write voltages and the obstacle of dedicated source lines, which increase the area and resistance of the memory array, leading to voltage drops and variations in applied voltages.
Innovation Solution
The implementation of a resistive memory array with shared bit lines or source lines, where multiple memory cells share a bit line or source line, reducing the number of lines in the column direction and increasing their width, thereby reducing resistance and maintaining uniform voltage application across the array.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dedicated source lines are configured in a one-to-one relationship with bit lines to achieve symmetry and reliable write operations, then write reliability is improved, but the area of the memory array increases and line resistance increases causing voltage drops
Solution Approach 1:
The patent merges multiple source lines into a shared source line that serves multiple bit lines. Instead of having dedicated source lines for each bit line, a single source line is designed to supply current to multiple memory cells through different word line selections, thereby reducing the total number of source lines and the overall area while maintaining write reliability through proper voltage control
2Reliability
If dedicated source lines are configured in a one-to-one relationship with bit lines to achieve symmetry and reliable write operations, then write reliability is improved, but the resistance of source lines increases causing voltage drops and variations
Solution Approach 1:
By combining multiple source line functions into a single shared source line, the patent reduces the total length and resistance of source lines. This merging approach decreases voltage drops and improves voltage uniformity across the memory array while maintaining reliable write operations through coordinated control of word lines and bit lines
3Area of stationary object
If the number of source lines is reduced by using shared source lines, then area efficiency is improved, but the current load on each source line increases
Solution Approach 1:
The patent segments the memory array into multiple blocks or regions, each served by its own shared source line. This segmentation allows the current load to be distributed across multiple source lines rather than concentrating all current through a single line, thereby managing power requirements while maintaining area efficiency
Solution Approach 2:
The patent employs periodic or sequential activation of different word lines and bit lines to access different memory cells. This time-division multiplexing approach ensures that not all memory cells are accessed simultaneously, thereby limiting the peak current load on shared source lines while maintaining high area efficiency
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for a more compact memory array with reduced resistance and uniform voltage application, enhancing the reliability of write and read operations while maintaining area efficiency.
Implementation Method 1
resistive memories are memories whose variable resistance elements are applied by pulse voltages, such that the variable resistance elements reversibly and non-volatilely become a high resistive state or a low resistive state to memorize information
Data Source
AI summary
The invention provides a resistive memory with better area efficiency without degrading reliability, which includes an array area, word lines, a local source line, bit lines, and a shared source line. In the array area, memory cells are arranged in a matrix, and each memory cells includes a variable resistance element and an accessing transistor. The word lines extend in a row direction of the array area and are connected to the memory cells in the row direction. The local source line extends in a column direction of the array area. The bit lines extend in the column direction and are connected to first electrodes of the memory cells in the column direction. The shared source line is connected to the local source line. The shared source line extends in the row direction and is connected to second electrodes of the memory cells in the row direction.