Vertical Resistive Memory Stack With High-k Layer for Shorter Channels
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Solution Overview
Problem
Resistive memory devices face challenges in reducing channel mastery and effective channel length, which affects their performance and efficiency in data storage and retrieval.
Innovation Solution
A resistive memory device is designed with a stack structure of interlayer insulating and conductive layers alternately stacked, featuring a hole with a gate insulating layer, channel layer, and variable resistance layer formed along the sidewall, and a high dielectric layer between the channel and gate insulating layers, which reduces channel mastery and effective channel length.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional resistive memory device structure is used, then the device can store data according to resistance change, but the channel mastery is excessive and the effective channel length is too long, affecting performance
Solution Approach 1:
The gate insulating layer is segmented into multiple portions (first gate insulating layer portion, second gate insulating layer portion, third gate insulating layer portion) along the sidewall of the hole. This segmentation allows different sections of the channel to be controlled independently, reducing the effective channel length while maintaining data storage reliability through the variable resistance layer.
Solution Approach 2:
The patent transitions from a planar structure to a three-dimensional structure by forming the gate insulating layer, channel layer, and variable resistance layer along the sidewall of a vertical hole. This vertical stacking arrangement reduces the effective channel length in the horizontal plane while maintaining functional integrity through the vertical dimension.
2Productivity
If a conventional resistive memory device structure is used, then the device can perform data storage operations, but the channel mastery is excessive, reducing efficiency
Solution Approach 1:
Different portions of the gate insulating layer are positioned at specific locations along the sidewall to locally control the channel. The first gate insulating layer portion is adjacent to the second conductive layer, the second portion is adjacent to the third conductive layer, and the third portion extends between them. This local quality approach reduces channel mastery in specific regions while maintaining overall device functionality and improving data retrieval efficiency.
Solution Approach 2:
The gate insulating layer structure is designed to dynamically control the channel conductivity through its multiple portions. By applying voltages to different conductive layers, the channel mastery can be adjusted dynamically, allowing the device to optimize between data storage and retrieval operations, thereby improving productivity without excessive complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively decreases channel mastery and channel length, enhancing the performance and efficiency of the resistive memory device in data storage and retrieval operations.
Implementation Method 1
a high dielectric layer formed between the channel layer and the gate insulating layer
Data Source
AI summary
The present technology relates to a resistive memory device and a method of manufacturing the same. The resistive memory device includes a stack structure in which a plurality of interlayer insulating layers and a plurality of conductive layers are alternately stacked, a hole passing through the stack structure in a vertical direction, a gate insulating layer, a channel layer, and a variable resistance layer sequentially formed along a sidewall of the hole, and a high dielectric layer formed between the channel layer and the gate insulating layer, the high dielectric layer being adjacent to the plurality of interlayer insulating layers.