Resistive Memory Sink Transistor Line Resistance Mismatch

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Solution Overview

Problem

Resistive memory devices face challenges in ensuring reliable read operations due to line resistance mismatches between normal memory cells and reference memory cells, which affect the sensing margin and accuracy of data storage states.

Innovation Solution

The implementation of a resistive memory device architecture that includes a memory cell array block, a reference cell array block, and a selection unit, with a column decoder and sink transistors to minimize line resistance mismatches by using reference cell currents to enhance sensing accuracy, allowing for reliable multi-bit data storage and read operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a single sink transistor is used per row line, then device complexity is reduced, but line resistance mismatches increase affecting sensing accuracy

Engineering Contradiction:

Improvenumber of sink transistorsVSAvoidsensing accuracy

Core Design Contradiction:

Device complexityVSMeasurement precision

Solution Approach 1:

Multiple sink transistors (first sink transistor and second sink transistor) are merged to serve a single row line, with both transistors coupled to the same row line. This configuration allows balanced current sinking from opposite ends of the bit line, reducing line resistance mismatches and improving sensing accuracy while maintaining reasonable device complexity.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

Sink transistors are strategically placed at different locations (opposite ends) of the bit line to address local resistance variations. The first sink transistor is coupled to one end of the row line while the second sink transistor is coupled to the opposite end, creating localized current sinking paths that compensate for position-dependent resistance differences.

Inventive Principle:

Principle #3Local quality

2Reliability

If reference cell array block is added to balance line resistance, then sensing margin improves, but device complexity increases

Engineering Contradiction:

Improvesensing marginVSAvoidmemory array structure

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The reference cell array block is configured to create equipotential conditions by matching the line resistance characteristics between normal and reference cells. Multiple sink transistors are used in both normal and reference cell paths to balance the potential distribution, ensuring that line resistance mismatches are minimized and sensing margin is improved.

Inventive Principle:

Principle #12Equipotentiality

Solution Approach 2:

A reference cell array block is created as a copy of the normal memory cell array block, with identical structural configuration including multiple sink transistors per row line. This copying approach ensures that line resistance characteristics are matched between normal and reference cells, improving sensing accuracy without requiring fundamentally different architectural approaches.

Inventive Principle:

Principle #26Copying

3Manufacturing precision

If multiple sink transistors are coupled to each row line, then line resistance mismatches are minimized, but manufacturing complexity increases

Engineering Contradiction:

Improveline resistance matchingVSAvoidtransistor fabrication

Core Design Contradiction:

Manufacturing precisionVSEase of manufacture

Solution Approach 1:

Multiple sink transistors are designed with identical structural and electrical characteristics, serving as universal current sinking elements. Each sink transistor follows the same fabrication pattern and configuration, allowing standardized manufacturing processes to be applied across all sink transistors in the array, thereby reducing manufacturing complexity despite the increased number of transistors.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS9311997B2Resistive memory device with word lines coupled to multiple sink transistors

Publication Date: 2016.04.12 SAMSUNG ELECTRONICS CO LTD

AI summary

A resistive memory device includes memory cell array blocks, a reference cell array block, two first and second sink transistors, and a word line. Each of the memory cell array blocks includes a row line, and the reference cell array block includes a reference row line. One of the first sink transistors is disposed between one end of the row line and a ground and the other of the first sink transistors is disposed between an opposite end of the row line and the ground. One of the second sink transistors is disposed between one end of the reference row line and the ground and the other of the second sink transistors is disposed between an opposite end of the reference row line and the ground. The word line is coupled to gates of the first and second sink transistors.