Resistive Memory Cell Layout for Reduced BEOL Step Height
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Solution Overview
Problem
The formation of non-volatile memory cells in integrated circuits often results in a step height between the memory cell and the periphery region, which reduces the process window of subsequent metallization layers, leading to defects and shorting issues due to the traditional dielectric layer structure.
Innovation Solution
A bottom electrode via is fabricated with a large critical dimension by enlarging the opening of the dielectric layer, allowing the non-volatile memory cell to be formed over a tapered portion of the dielectric layer, thereby reducing the step height and improving the process window by ensuring the memory cell's sidewalls land on a slanted sidewall of the dielectric layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a traditional dielectric layer structure is used, then the memory cell can be formed with standard dimensions, but a step height is created between the memory cell and periphery region, reducing the process window of subsequent metallization layers
Solution Approach 1:
The dielectric layer is configured with different thicknesses in different regions: a first thickness in the periphery region and a second (reduced) thickness in the memory region. This local variation in dielectric thickness eliminates the step height between regions while maintaining the structural integrity and electrical isolation functions of the dielectric layer, thereby improving the process window for subsequent metallization without compromising manufacturing precision
Solution Approach 2:
The solution transitions from a two-dimensional planar dielectric structure to a three-dimensional varying thickness structure. By introducing vertical dimension variation (thickness gradient) across the dielectric layer, the patent eliminates the horizontal step height issue while maintaining effective isolation, thus resolving the contradiction between shape uniformity and process window
2Shape
If the opening of the dielectric layer is enlarged to fabricate a bottom electrode via with a large critical dimension, then the step height is reduced, but the dielectric layer structure becomes more complex
Solution Approach 1:
The patent changes the geometric parameter of the dielectric layer from uniform thickness to variable thickness (thinner in memory region, thicker in periphery). This parameter change allows the bottom electrode via to be formed with a larger critical dimension that overlaps with the periphery region, reducing step height while avoiding the need for complex multi-layer dielectric structures or additional processing steps
3Manufacturing precision
If spacers are used to pattern memory cells, then the patterning precision is improved, but the manufacturing cost increases
Solution Approach 1:
The patent removes the spacer component from the patterning process entirely. By designing the bottom electrode via with a sufficiently large critical dimension that directly overlaps with the periphery region, the method achieves effective patterning without requiring the additional spacer layer and associated deposition/etching steps, thereby reducing manufacturing complexity and cost while maintaining adequate patterning precision
Data Source
AI summary
A method for fabricating an integrated circuit is provided. The method includes depositing a dielectric layer over a conductive feature; etching an opening in the dielectric layer to expose the conductive feature, such that the dielectric layer has a tapered sidewall surrounding the opening; depositing a bottom electrode layer into the opening in the dielectric layer; depositing a resistance switch layer over the bottom electrode layer; patterning the resistance switch layer and the bottom electrode layer respectively into a resistance switch element and a bottom electrode, in which a sidewall of the bottom electrode is landing on the tapered sidewall of the dielectric layer.