Multi-Level Resistive Memory Transistor Integration
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Solution Overview
Problem
Current resistive memory devices face challenges in achieving high integration density, particularly in the production of resistive memory cells that require complex masking and etching processes, which can lead to inefficiencies and potential damage to dielectric regions.
Innovation Solution
A method is developed to produce devices with transistors distributed over multiple levels, where a resistive memory cell is formed by creating a dielectric region on a conductor portion of a connection element, allowing for the assembly of a semiconductor layer without prior etching, and forming electrodes on this dielectric region, thereby simplifying the process and avoiding the need for complex masking and etching steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If complex masking and etching processes are used to form resistive memory cells, then manufacturing precision can be achieved, but device complexity and production time increase significantly
Solution Approach 1:
The dielectric region is formed on the conductor portion before the opening is created through the second insulator layer. This preliminary formation eliminates the need for subsequent masking or etching operations to create the dielectric region, directly resolving the contradiction by achieving precise memory cell formation without complex processes
Solution Approach 2:
The invention extracts and removes the complex masking and etching steps from the production process. By forming the dielectric region in advance on the conductor portion, the patent eliminates these harmful complex operations while maintaining manufacturing precision through the preliminary structured arrangement
2Ease of manufacture
If etching is performed on dielectric regions to form openings, then memory cell structure can be created, but damage to dielectric regions and reliability decrease occur
Solution Approach 1:
The dielectric region is formed before the opening is created, allowing the opening to be formed through the second insulator layer without requiring etching of the dielectric region itself. This preliminary arrangement protects the dielectric region from damage while still enabling easy opening formation
Solution Approach 2:
The invention applies preliminary anti-action by forming the dielectric region in advance on the conductor portion, which prevents the need for subsequent etching operations that would damage the dielectric. This preemptive structuring avoids the harmful etching action before it can occur
3Quantity of substance
If transistors are distributed over multiple levels with resistive memory cells, then integration density improves, but manufacturing process complexity increases
Solution Approach 1:
The patent distributes transistors over multiple vertical levels and forms resistive memory cells between these levels, transitioning from a planar to a three-dimensional architecture. This dimensional change achieves higher integration density while the preliminary dielectric formation simplifies the manufacturing process for this complex multi-level structure
Solution Approach 2:
The device is segmented into multiple levels with transistors distributed across different planes, and resistive memory cells formed between specific levels. This segmentation enables high integration density while the standardized preliminary dielectric formation process reduces the complexity of manufacturing each segmented unit
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances integration density and simplifies the production process, reducing the risk of damage to dielectric regions and improving the reliability of resistive memory cells, such as OxRAM, by allowing full wafer deposition and molecular bonding without prior etching, leading to more efficient and reliable memory devices.
Implementation Method 1
The dielectric layer is not etched to constitute the dielectric region intercalated between the electrodes of the memory cell
Implementation Method 2
The dielectric layer is not etched to constitute the dielectric region intercalated between the electrodes of the memory cell
Implementation Method 3
The support including the semiconductor layer in which the second transistor is formed may for its part be assembled by molecular bonding
Data Source
AI summary
Method for producing a device with transistors distributed over several levels and provided with a resistive memory cell having an electrode formed of a conductor portion belonging to a connection element connected to a transistor of a given level.