Resistive Memory Verify Write Pulse Control
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Solution Overview
Problem
Current resistive memory devices face inefficiencies in verify write operations due to limitations in current-voltage characteristics, which affect the accuracy and speed of programming resistance states in memory cells.
Innovation Solution
A method is introduced for operating resistive memory devices that involves applying write pulses and verify pulses to adjust resistance states within specific reference ranges, using verify write current or voltage pulses to correct resistance levels, ensuring accurate programming by comparing initial resistances and adjusting pulse amplitudes and widths accordingly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a write pulse is applied to program resistance states in memory cells, then the memory cells can be programmed to target resistance states, but the verify write operation efficiency is insufficient due to limitations in current-voltage characteristics
Solution Approach 1:
The patent segments the verify write operation into two distinct phases: a first verify write operation using a current pulse and a second verify write operation using a voltage pulse. This segmentation allows each operation to be optimized for different resistance states, improving overall efficiency while maintaining programming accuracy. The current pulse is used when resistance is above the target state, and the voltage pulse is used when resistance is below the target state.
Solution Approach 2:
The patent dynamically adjusts the verify write operation based on real-time resistance measurements. The controller selectively applies different types of pulses (current or voltage) depending on the measured resistance state of the memory cell. This dynamic adaptation overcomes the limitations of fixed current-voltage characteristics and improves verify write efficiency.
2Measurement precision
If verify pulses are applied to read resistance of memory cells, then resistance states can be monitored, but the operation requires multiple steps reducing speed
Solution Approach 1:
The patent performs a preliminary read operation to determine the initial resistance state of the memory cell before applying the verify write pulse. This preliminary action allows the controller to select the appropriate pulse type (current or voltage) in advance, streamlining the subsequent verify write operation and improving overall speed while maintaining measurement precision.
Solution Approach 2:
The patent implements a feedback mechanism where the resistance measurement result directly controls the selection of the verify write pulse type. The controller uses the measured resistance value to feedback-select whether to apply a current pulse or voltage pulse, creating a closed-loop system that optimizes both precision and speed.
3Manufacturing precision
If write pulses are applied to adjust resistance states, then memory cells can be programmed, but resistance states may fall outside reference ranges requiring correction
Solution Approach 1:
The patent changes the parameter type of the verify write pulse based on the measured resistance state. When resistance is above the target state, a current pulse is applied; when resistance is below the target state, a voltage pulse is applied. This parameter change strategy ensures precise resistance control while managing complexity through a systematic decision-making process.
Solution Approach 2:
The patent applies different qualities of pulses (current vs. voltage) to different local conditions of the memory cell resistance state. Each resistance condition (above or below target) receives a specifically tailored pulse type, ensuring optimal correction efficiency while maintaining overall system manageability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the efficiency and accuracy of verify write operations by precisely controlling resistance states in memory cells, improving the overall performance and reliability of resistive memory devices.
Implementation Method 1
applying a write pulse to each of the plurality of memory cells such that each of the plurality of memory cells has a target resistance state between a first reference resistance and a second reference resistance higher than the first reference resistance
Data Source
AI summary
In operating a resistive memory device including a number of memory cells, a write pulse is applied to each of the plurality of memory cells such that each of the memory cells has a target resistance state between a first reference resistance and a second reference resistance higher than the first reference resistance. The resistance of each of the memory cells is read by applying a verify pulse to each of the plurality of memory cells. A verify write current pulse is applied to each of the memory cells that has resistance higher than the second reference resistance, and a verify write voltage pulse is applied to each of the memory cells that has resistance lower than the first reference resistance.