Resistive Memory Device with Vertical Resistance Profile
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Solution Overview
Problem
High integration of semiconductor memory devices leads to thermal interference between adjacent conductive lines, causing erroneous operations due to heat transfer between resistive memory material states, which are not effectively managed in conventional designs.
Innovation Solution
A semiconductor memory device with a resistive memory material layer having a vertically non-uniform specific resistance profile, formed by depositing impurity layers at different depths to create alternating high resistance regions, reducing heat transfer between adjacent programming regions through increased vertical distance between them.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the gap between adjacent conductive lines is reduced to increase integration, then device integration is improved, but thermal interference between adjacent intersection points increases
Solution Approach 1:
The patent applies local quality by creating vertically non-uniform specific resistance profiles in the resistive memory material layer. Different regions of the memory material have different resistance characteristics - with high resistance regions positioned at specific vertical locations to act as thermal barriers. This local variation in resistance properties allows heat to be contained within operational portions while preventing thermal interference with adjacent non-operational portions, thereby enabling reduced gap between conductive lines without suffering from thermal interference.
Solution Approach 2:
The patent transitions from a two-dimensional uniform resistive memory material layer to a three-dimensional structure with vertically non-uniform resistance profiles. By introducing vertical dimensionality variations in the resistance characteristics (through multiple layers or depth-dependent resistance modulation), the patent creates thermal isolation barriers in the vertical dimension that prevent lateral heat spread between adjacent intersection points, thus enabling higher integration without thermal interference.
2Ease of operation
If heat is generated in operational portions of resistive memory material, then programming or deletion operation is achieved, but heat transfers to adjacent non-operational portions causing erroneous operation
Solution Approach 1:
The patent implements local quality by positioning high resistance regions within the resistive memory material layer at specific vertical locations. These localized high resistance regions serve as thermal barriers that confine heat generation to the operational portions during programming or deletion operations. The heat is prevented from spreading vertically to adjacent non-operational portions, thereby maintaining reliable operation without erroneous activation while still achieving the required programming functionality.
Solution Approach 2:
The patent introduces high resistance regions as intermediary thermal barriers within the resistive memory material layer. These intermediary regions act as thermal insulators between operational portions (where heat is generated during programming) and adjacent non-operational portions. The high resistance regions mediate the thermal interaction by blocking heat flow, thus preventing erroneous operation while allowing the programming operation to proceed normally.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Minimizes thermal interference and erroneous operations by maintaining a sufficient distance between programming regions, facilitating higher integration and reducing manufacturing costs while preventing incorrect activation of non-operational states.
Implementation Method 1
Application of an electrical pulse to the resistive memory material may generate heat, thereby setting the resistive memory material into an amorphous state or into a crystalline state with respect to its resistive state.
Implementation Method 2
Application of an electrical pulse to the resistive memory material may generate heat
Implementation Method 3
the resistive memory material having a vertically non-uniform specific resistance profile with respect to the substrate... reducing heat transfer between adjacent programming regions through increased vertical distance between them
Data Source
AI summary
A semiconductor memory device includes first conductive lines on a substrate, an interlayer insulating layer with a plurality of via holes on the substrate, second conductive lines on the interlayer insulating layer, and a resistive memory material in the via holes and electrically connected to the first and second conductive lines, the resistive memory material having a vertically non-uniform specific resistance profile with respect to the substrate.