Resistive Memory Arrays Using Dummy-Transistor Voltage Calibration
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Solution Overview
Problem
Current resistive random access memory (RRAM) faces issues with low operating speed and is not conducive to miniaturization due to inconsistent transistor driving capabilities and the need for frequent adjustments of bit line voltage during forming and write operations, which are influenced by process variations.
Innovation Solution
A resistive memory apparatus with a memory cell array, dummy transistor, and control circuit that determines bit line voltage based on the saturation current of the dummy transistor to accurately drive memory cells, enhancing operating speed and facilitating miniaturization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the bit line voltage is adjusted multiple times during forming and write operations to accommodate transistor driving capability variations, then the memory cell can be written to a specific resistance state, but the operating speed is reduced
Solution Approach 1:
The patent applies preliminary action by measuring the saturation current of the transistor before performing forming or write operations. This advance measurement allows the system to determine the appropriate bit line voltage in advance, eliminating the need for multiple voltage adjustments during the actual operations, thereby improving operating speed while maintaining write accuracy.
2Reliability
If additional circuits are configured to compensate for transistor driving capability variations, then the cell current variation is reduced, but the device complexity increases and miniaturization is hindered
Solution Approach 1:
The patent applies parameter changes by measuring the saturation current (a key parameter) of the transistor and using this information to dynamically adjust the bit line voltage. This approach compensates for transistor driving capability variations without requiring additional complex circuits, as it leverages existing measurement and control mechanisms to achieve cell current consistency.
3Reliability
If the bit line voltage is readjusted in each write operation to account for transistor variations, then the write operation succeeds, but the productivity decreases
Solution Approach 1:
The patent applies preliminary action by performing saturation current measurement and bit line voltage determination before each write operation. This advance preparation ensures that the correct voltage is applied from the start, guaranteeing write operation success while minimizing the time spent on voltage adjustments, thereby improving overall operating efficiency and productivity.
4Ease of manufacture
If the transistor driving capability is not known before filament formation, then the forming procedure can be simplified, but the bit line voltage cannot be accurately provided
Solution Approach 1:
The patent applies preliminary action by measuring the saturation current of the transistor before the filament formation process. This measurement provides accurate information about the transistor's driving capability, enabling the system to determine the precise bit line voltage needed for successful forming and write operations, thereby achieving both manufacturing simplicity and voltage accuracy.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution allows for precise application of bit line voltage, increasing operating speed and reducing power consumption while overcoming driving limitations, thus supporting efficient write operations and miniaturization.
Implementation Method 1
the resistive switching element can be repeatedly switched between high and low resistance states for storing data
Implementation Method 2
oxygen vacancy and oxygen ions are generated in the resistive switching layer to form a current path, and the resistive switching element is changed from the high resistance state (HRS) to the low resistance state (LRS) to form a conductive filament
Data Source
AI summary
A resistive memory apparatus including a memory cell array, at least one dummy transistor and a control circuit is provided. The memory cell array includes a plurality of memory cells. Each of the memory cells includes a resistive switching element. The dummy transistor is electrically isolated from the resistive switching element. The control circuit is coupled to the memory cell array and the dummy transistor. The control circuit is configured to provide a first bit line voltage, a source line voltage and a word line voltage to the dummy transistor to drive the dummy transistor to output a saturation current. The control circuit is further configured to determine a value of a second bit line voltage for driving the memory cells according to the saturation current. In addition, an operating method and a memory cell array of the resistive memory apparatus are also provided.