Resistive Memory Voltage Divider Interpretation Circuit
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Solution Overview
Problem
Conventional crossbar memory structures require multiple comparisons and reference resistors to determine the resistive state of memristors, leading to complexity and cost, and are affected by memory state dependence and parasitic resistances.
Innovation Solution
A resistive memory structure with a series-connected resistor forming a voltage divider and an interpretation circuit to determine the resistive state based on the voltage at the electrical node, reducing the number of comparators needed and mitigating leakage and parasitic resistance issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple comparators and reference resistors are used to determine resistive state, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent extracts and eliminates the need for multiple reference resistors and comparators by using a single reference resistor combined with a voltage comparator that evaluates multiple voltage divider configurations. This reduces the complex measurement system to essential components while maintaining measurement precision through sequential voltage comparison.
Solution Approach 2:
A single voltage comparator performs multiple comparison functions by evaluating different voltage divider configurations (different resistor combinations) to determine multiple resistive states. This multi-functional approach replaces what would traditionally require multiple dedicated comparators, reducing device complexity while maintaining measurement capabilities.
2Ease of operation
If conventional read methodologies are used, then data can be read from memory cells, but parasitic resistances and memory state dependence affect measurement accuracy
Solution Approach 1:
The patent implements a feedback mechanism where the voltage comparator evaluates voltage divider configurations and uses the results to determine resistive states while compensating for parasitic effects. The system uses the measured voltage information to adjust and refine the determination of memory cell states, effectively correcting for parasitic resistance and memory state dependence through iterative evaluation.
3Quantity of substance
If ultra-dense crossbar memory structures are implemented, then storage density is improved, but leakage current and parasitic resistances increase
Solution Approach 1:
The patent converts the harmful effects of parasitic resistances and leakage currents into beneficial information by using them as part of the measurement model. The voltage comparator system evaluates voltage dividers in a way that accounts for these parasitic effects, transforming them from sources of error into measurable parameters that can be compensated for in the resistive state determination process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the determination of resistive states, reduces the number of comparators required, and minimizes the impact of leakage and parasitic resistances, enabling efficient read and write operations in ultra-dense memristor memory structures.
Implementation Method 1
a resistor electrically connected in series to the resistive memory element thereby forming a voltage divider and electrical node therebetween
Data Source
AI summary
A resistive memory structure comprises at least one resistive memory element configured to store one or more bits of data and a circuit electrically connected to the resistive memory element for use in performing at least one of a read or write operation on the at least one resistive memory element. The circuit includes a resistor electrically connected in series to the resistive memory element thereby forming a voltage divider and electrical node therebetween, and an interpretation circuit electrically connected to the electrical node formed between the resistive memory element and the resistor. The interpretation circuit is configured to interpret a voltage at the electrical node and to determine a resistive state of the resistive memory element based on the voltage at the electrical node.


