Resistive Memory ECC Decoding With Weak-Bit Inversion
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Solution Overview
Problem
Resistive memories, such as RRAMs, face challenges with high error rates due to cell-to-cell non-uniformity and relaxation phenomena, which can lead to incorrect resistance states and data loss, especially in 1T1R and 2T2R memory types.
Innovation Solution
The method involves identifying and utilizing 'weak-bits' by comparing resistance values with slightly higher and lower reference values, and inverting these weak-bits during error correction to improve the decoding process, allowing for correction of previously uncorrectable errors without increasing the number of check bits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional ECC decoding is used, then decoding speed is maintained, but error correction capacity is insufficient for resistive memory errors
Solution Approach 1:
The patent performs preliminary identification of weak-bits by comparing resistance values with reference values before the main ECC decoding process. This preliminary action prepares the data in advance, allowing the subsequent decoding to achieve higher error correction capacity without proportionally increasing overall complexity
Solution Approach 2:
The decoding process is segmented into distinct stages: weak-bit identification phase, inversion phase, and main ECC decoding phase. Each stage handles specific tasks independently, improving overall error correction capacity while managing complexity through modular processing
2Reliability
If more check bits are added to increase error correction capacity, then more errors can be corrected, but storage density and write efficiency decrease
Solution Approach 1:
The patent changes the parameter of resistance comparison by introducing multiple reference values (first reference value and second reference value) that are slightly higher and lower than the nominal reference. This parameter change enables weak-bit identification without requiring additional check bits, thereby maintaining write efficiency while improving error correction capacity
3Speed
If resistance threshold comparison is used for reading, then read speed is fast, but measurement precision is insufficient to distinguish weak-bits
Solution Approach 1:
The patent applies local quality by using different reference values for different comparison purposes: a first reference value slightly higher than nominal and a second reference value slightly lower than nominal. This localized adjustment of reference values enables precise identification of weak-bits while maintaining fast read operation speed
Data Source
AI summary
A device and a method for reading a code word in a resistive memory protected by an ECC where each memory cell includes resistive devices for storing a bit of a code word. The method allows the selection, as a function of the value of a syndrome, of a corrected word following a first decoding process without inversion of weak-bits or of a corrected word following a second decoding process with inversion of weak-bits. If the computed syndrome determines that the first decoding process has indicated an uncorrectable error or determines that the second decoding process has indicated neither an uncorrectable error nor an n-error (i.e., a maximum of n erroneous bits per code word), the selected word is the corrected word with inversion of the weak-bits. Otherwise, the selected word is the corrected word without inversion of the weak-bits.