Resistive Memory Erase Using a Weak Program State
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Solution Overview
Problem
Resistive-switching memory cells face issues with erase failures due to the conductive filament reverting to a low resistance state over time, leading to data loss and reduced memory longevity.
Innovation Solution
An improved erase process involving a combination of erase and weak program cycles is employed, forming a weakly set filament that drifts to a higher resistance state, mitigating erase failures by ensuring the memory cell remains in a stable reset state.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a standard erase process is applied to reset the memory cell to a high resistance state, then the memory cell is returned to an erase state, but the conductive filament may revert to a low resistance state over time causing erase failure
Solution Approach 1:
A weak program pulse is applied immediately after the erase process while the memory cell is in the erase state. This preliminary action creates a weakly set filament that positions the resistance in an intermediate state, preventing the filament from completely reverting to the low resistance state and thereby maintaining data retention over time.
Solution Approach 2:
The invention introduces a new resistance state parameter - the weakly set state with intermediate resistance value between the fully programmed low resistance state and the erased high resistance state. By controlling the filament resistance to this intermediate value through the weak program pulse, the system achieves improved erase state stability and prevents erase failure.
2Manufacturing precision
If multiple erase cycles are performed to ensure complete reset, then erase thoroughness is improved, but processing time and energy consumption increase
Solution Approach 1:
The weak program pulse serves as a preliminary corrective action that ensures complete erase state achievement in a single cycle rather than requiring multiple repetitive erase cycles. This approach achieves erase completeness more efficiently by preventing partial erasure issues that would otherwise require additional cycles to resolve.
Solution Approach 2:
Instead of performing discrete, repetitive erase cycles with idle periods in between, the invention applies a continuous useful action by immediately following the erase process with a weak program pulse. This continuous action ensures complete erasure in one uninterrupted sequence, reducing total processing time while maintaining erase thoroughness.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed method significantly reduces erase disturb bits and enhances the longevity of non-volatile resistive-switching memory devices by maintaining a stable high resistance state, thereby improving data retention.
Implementation Method 1
Resistive-switching memory cells can be configured to have multiple states with measurably distinct resistance values
Data Source
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AI summary
Improved erase techniques enhance longevity of two-terminal non-volatile memory and can mitigate or avoid erase state memory failures. An erase process can include performing an erase operation(s) on a two-terminal memory cell, followed by a weak program operation. An erase-verify process can determine whether the memory cell has a read current within a target range. In one or more embodiments, additional erase and weak program cycles can be implemented to initiate a weakly programmed state that can be defined as an erase state. The weakly programmed state can be configured so that drift or diffusion over time results in higher resistance not reversion to a low resistance state, to mitigate or avoid erase failure of the two-terminal memory cell.