Resistive Memory Write Latency and Power Optimization
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Solution Overview
Problem
Current resistive memory devices face challenges in reducing write latency and power consumption during selective write operations, particularly due to the need for pre-read and comparison operations, which increase overall write time and power usage.
Innovation Solution
A resistive memory device and method that determines whether write data is in a set or reset state, applying a first pulse when in a set state and selectively applying a second pulse based on a comparison with pre-read data, thereby skipping unnecessary operations and reducing latency and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If pre-read and comparison operations are performed before write operations, then data integrity is ensured, but write latency increases
Solution Approach 1:
The patent applies preliminary action by determining the state of write data before initiating the write operation. The peripheral circuit detects whether write data is in a set state or reset state and prepares the appropriate pulse in advance, eliminating the need for post-write verification and reducing overall write latency while maintaining data integrity
Solution Approach 2:
The patent extracts the unnecessary pre-read and comparison operations from the write sequence. By directly determining the state of write data and selectively applying pulses based on this determination, the patent removes the time-consuming pre-read and comparison steps that were previously required to ensure data integrity
2Reliability
If pre-read and comparison operations are performed before write operations, then correct data writing is ensured, but power consumption increases
Solution Approach 1:
The peripheral circuit performs preliminary determination of the write data state and prepares the appropriate pulse (first pulse for set state, second pulse for reset state) in advance. This eliminates the need for power-consuming pre-read and comparison operations while ensuring correct data writing through selective pulse application
Solution Approach 2:
The patent removes the power-consuming pre-read and comparison operations from the write sequence. By directly determining the state of write data and selectively applying pulses based on this determination, the patent eliminates unnecessary power consumption while maintaining correct data writing
3Reliability
If heat-anneal process is applied to all memory cells, then data reliability is improved, but write time and power consumption increase
Solution Approach 1:
The patent applies local quality by selectively applying the heat-anneal process only to memory cells that require it. Based on the determination of write data state, the peripheral circuit applies the first pulse (with heat-anneal) only when write data is in the set state, while skipping the heat-anneal process when write data is in the reset state, thereby reducing overall write time and power consumption while maintaining data reliability where needed
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution reduces write latency and power consumption by omitting unnecessary pre-read operations and eliminating separate heat-anneal processes, especially for memory cells in a set state, while maintaining data integrity.
Implementation Method 1
The resistance of materials consisting of next-generation semiconductor memory elements may be varied in accordance with a voltage or current supplied to the memory devices
Implementation Method 2
a phase-change random access memory (PRAM) using a phase-change material
Data Source
AI summary
An operation method of a resistive memory device includes receiving write data and an address; determining whether the write data is in a first state or in a second state; applying a first pulse to a target memory cell corresponding to the address, among a plurality of memory cells, when the write data is in the first state; and selectively applying, when the write data is in the second state, a second pulse to the target memory cell according to a comparison result of the write data and pre-read data which is pre-stored data read from the target memory cell.