Resistive MLC Memory Cell Layout for In-Memory Computing
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Solution Overview
Problem
Existing integrated circuit (IC) devices face challenges in efficiently performing computing operations within memory cells due to bottlenecks in data movement between memory and processors, which affect performance and energy efficiency.
Innovation Solution
The implementation of a memory device with multi-level cell (MLC) memory cells that utilize programmable resistance values in memory elements, allowing for in-memory computing (CiM) operations, where data processing is performed directly within the memory array, reducing the need for back-and-forth data movement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is moved back and forth between memory and processors for computing operations, then data processing can be performed using separate storage and computing units, but performance and energy efficiency deteriorate due to data movement bottlenecks
Solution Approach 1:
The patent merges memory storage and computing functions into a single integrated structure by forming resistive memory cells directly within the memory array, enabling in-memory computing operations. This eliminates the need for separate data movement between distinct memory and processor units, thereby improving both computation performance and energy efficiency simultaneously.
2Adaptability or versatility
If multi-level cell memory with programmable resistance values is implemented, then in-memory computing operations become enabled, but device complexity increases
Solution Approach 1:
The patent utilizes programmable resistance values as a key parameter to enable multi-level cell memory functionality. By varying the resistance states of memory elements within the existing memory cell structure, the system achieves in-memory computing capability without fundamentally redesigning the hardware architecture, thus managing device complexity while enhancing adaptability.
3Loss of time
If data processing is performed directly within the memory array, then the need for back-and-forth data movement is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent replaces mechanical data movement operations with electrical resistance-based computing operations performed directly within the memory array. By using resistive memory elements that can be programmed to different resistance states, the system performs computations in-place without physical data movement, thereby reducing time loss while the manufacturing precision is managed through established resistive memory fabrication processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances computation performance and energy efficiency by enabling computing operations within the memory cells, particularly suitable for applications like artificial intelligence and neural networks, by leveraging the linearistic resistance variations for reliable data storage and processing.
Implementation Method 1
memory elements configured with programmable resistance values
Data Source
AI summary
An integrated circuit (IC) device includes memory cells each including first through fourth memory elements. The first memory element is physically arranged, along a first axis, between a bit line and a first auxiliary conductive line. The second memory element is physically arranged, along the first axis, between a second auxiliary conductive line and a first conductor. The first and second memory elements are arranged in a first row along the first axis. The third memory element is physically arranged, along the first axis, between the first auxiliary conductive line and a second conductor electrically coupled to the first conductor. The fourth memory element is physically arranged, along the first axis, between the bit line and the second auxiliary conductive line. The third and fourth memory elements are arranged, along the first axis, in a second row spaced from the first row along an axis transverse to the first axis.